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Pub. No.:    WO/2013/153850    International Application No.:    PCT/JP2013/053451
Publication Date: Fri Oct 18 01:59:59 CEST 2013 International Filing Date: Fri Feb 15 00:59:59 CET 2013
IPC: H03K 19/177
H01L 21/82
Applicants: TAIYO YUDEN CO.,LTD.
Inventors: SATOU Masayuki
佐藤 正幸
SATO Koshi
佐藤 幸志
[Problem] To enable production with standard processes, to enable the use of memory cell units as a synchronous memory, and to eliminate the need for expensive semiconductor designing. [Solution] Provided is a semiconductor device comprising a plurality of logic units that constitute an array and that are connected to one another, wherein: each logic unit has a pair of first and second memory cell units; each of the first and second memory cell units operates as a logic element when truth table data configured to output, to a data line, a logic computation of input values specified by a plurality of addresses is written in, or operates as a connection element when truth table data configured to output an input value specified by a certain address to a data line connected to the address of another memory cell unit is written in; a sequential circuit that is in synchronization with a clock is provided after the first memory cell unit; and the logic unit has, for each pair of memory cell units, a selection unit that selectively outputs an address to the first or second memory cell unit in accordance with an operation switching signal.