Some content of this application is unavailable at the moment.
If this situation persist, please contact us atFeedback&Contact
1. (WO2013153742) SEMICONDUCTOR DEVICE
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2013/153742 International Application No.: PCT/JP2013/001618
Publication Date: 17.10.2013 International Filing Date: 12.03.2013
Chapter 2 Demand Filed: 07.02.2014
IPC:
H01L 25/065 (2006.01) ,H01L 23/12 (2006.01) ,H01L 25/07 (2006.01) ,H01L 25/18 (2006.01) ,H01L 27/10 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
065
the devices being of a type provided for in group H01L27/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
12
Mountings, e.g. non-detachable insulating substrates
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
07
the devices being of a type provided for in group H01L29/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
18
the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/-H01L51/160
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
Applicants:
パナソニックIPマネジメント株式会社 PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD. [JP/JP]; 大阪府大阪市中央区城見2丁目1番61号 1-61, Shiromi 2-chome, Chuo-ku, Osaka-shi, Osaka 5406207, JP
Inventors:
木下 智博 KINOSHITA, Tomohiro; null
高橋 英治 TAKAHASHI, Eiji; null
小松 直樹 KOMATSU, Naoki; null
瓜生 一英 URIU, Kazuhide; null
Agent:
鮫島 睦 SAMEJIMA, Mutsumi; 大阪府大阪市北区角田町8番1号梅田阪急ビルオフィスタワー青山特許事務所 AOYAMA & PARTNERS, Umeda Hankyu Bldg. Office Tower, 8-1, Kakuda-cho, Kita-ku, Osaka-shi, Osaka 5300017, JP
Priority Data:
2012-09020511.04.2012JP
Title (EN) SEMICONDUCTOR DEVICE
(FR) DISPOSITIF À SEMICONDUCTEUR
(JA) 半導体装置
Abstract:
(EN) This semiconductor device is provided with a first semiconductor chip, and a second semiconductor chip, which is connected on the first semiconductor chip by chip-on-chip connection. When the semiconductor device is viewed from the direction perpendicular to the upper surface of the second semiconductor chip, the outer shape of the second semiconductor chip is larger than the outer shape of the first semiconductor chip. On the upper surface of the first semiconductor chip, a plurality of first semiconductor chip electrode terminals are provided, and the first semiconductor chip electrode terminals include one or a plurality of first shielded terminals, which are covered with the second semiconductor chip, and one or a plurality of first open terminals, which are not covered with the second semiconductor chip.
(FR) La présente invention concerne un dispositif à semiconducteur muni d'une première puce à semiconducteur et d'une deuxième puce à semiconducteur branchée sur la première puce à semiconducteur par liaison puce sur puce. Lorsque le dispositif à semiconducteur est vu depuis une direction perpendiculaire à la surface supérieure de la deuxième puce à semiconducteur, le contour extérieur de la deuxième puce à semiconducteur est plus grand que le contour extérieur de la première puce à semiconducteur. Sur la surface supérieure de la première puce à semiconducteur se trouve une pluralité de bornes d'électrodes de première puce à semiconducteur, et les bornes d'électrodes de la première puce à semiconducteur comprennent une ou plusieurs premières bornes masquées, qui sont recouvertes par la deuxième puce à semiconducteur, et une ou plusieurs premières bornes ouvertes, qui ne sont pas recouvertes par la deuxième puce à semiconducteur.
(JA)  半導体装置は、第1半導体チップと、第1半導体チップ上にチップ・オン・チップ接続された第2半導体チップとを備え、第2半導体チップの上面に垂直な方向から見た場合、第2半導体チップの外形は、第1半導体チップの外形よりも大きく、第1半導体チップの上面には複数の第1半導体チップ電極端子が設けられており、複数の第1半導体チップ電極端子は、第2半導体チップで覆われた1又は複数の第1遮蔽端子と、第2半導体チップで覆われていない1又は複数の第1開放端子とを含む。
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)