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1. WO2013150260 - SRAM DEVICE WITH MEMORY CELLS EACH HAVING A DEDICATED ACCESS CONNECTION TO|COMMON READ/WRITE CIRCUIT

Publication Number WO/2013/150260
Publication Date 10.10.2013
International Application No. PCT/GB2013/000150
International Filing Date 03.04.2013
IPC
G11C 11/412 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
41forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
412using field-effect transistors only
G11C 11/419 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
41forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
413Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
417for memory cells of the field-effect type
419Read-write circuits
G11C 5/02 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
5Details of stores covered by group G11C11/63
02Disposition of storage elements, e.g. in the form of a matrix array
CPC
G11C 11/412
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
41forming ; static; cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
412using field-effect transistors only
G11C 11/419
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
41forming ; static; cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
413Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing, power reduction
417for memory cells of the field-effect type
419Read-write [R-W] circuits
G11C 5/025
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
5Details of stores covered by G11C11/00
02Disposition of storage elements, e.g. in the form of a matrix array
025Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
H01L 21/8239
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78with subsequent division of the substrate into plural individual devices
82to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822the substrate being a semiconductor, using silicon technology
8232Field-effect technology
8234MIS technology ; , i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
8239Memory structures
H01L 27/11
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
11Static random access memory structures
Applicants
  • SILICON BASIS LTD. [GB]/[GB]
Inventors
Priority Data
1206037.204.04.2012GB
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) SRAM DEVICE WITH MEMORY CELLS EACH HAVING A DEDICATED ACCESS CONNECTION TO|COMMON READ/WRITE CIRCUIT
(FR) DISPOSITIFS MÉMOIRES STATIQUES À ACCÈS ALÉATOIRE
Abstract
(EN)
The present application relates to an improved static random access memory (SRAM) device having a plurality of storage cells and a separate read/write circuit. Each of the plurality of storage cells is connected to a read/write data node of the read/write circuit by a dedicated connection, and an access switch which permits read/write access to the storage cell. The dedicated connection exhibits a greater capacitance than the read/write data node of the read/write circuit, such that the primary read mechanism of the SRAM is charge equalisation. The SRAM device also includes a write data connection and means for connecting the write data connection to the read/write node of the read/write circuit, to permit data to be written to the plurality of storage cells. Write assist techniques are disclosed which assist writing of a '1' to the plurality of storage cells.
(FR)
La présente invention concerne un dispositif mémoire statique à accès aléatoire (SRAM) ayant une pluralité de cellules de stockage et un circuit de lecture/écriture séparé. Chacune des cellules de stockage est connectée à un noeud de données de lecture/écriture du circuit de lecture/écriture par une connexion dédiée et un commutateur d'accès qui permet un accès en lecture/écriture à la cellule de stockage. La connexion dédiée présente une capacité plus grande que le noeud de données de lecture/écriture du circuit de lecture/écriture, de telle sorte que le mécanisme de lecture primaire de la SRAM est l'égalisation de charge. Le dispositif SRAM comprend également une connexion de données d'écriture et des moyens pour connecter la connexion de données d'écriture au noeud de lecture/écriture du circuit de lecture/écriture afin de permettre l'écriture de données sur la pluralité de cellules de stockage. L'invention concerne des techniques d'aide à l'écriture qui aident à l'écriture d'un '1' sur la pluralité de cellules de stockage.
Also published as
Latest bibliographic data on file with the International Bureau