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1. (WO2013147970) CYCLE ACCURATE AND CYCLE REPRODUCIBLE MEMORY FOR AN FPGA BASED HARDWARE ACCELERATOR

Pub. No.:    WO/2013/147970    International Application No.:    PCT/US2013/020505
Publication Date: Fri Oct 04 01:59:59 CEST 2013 International Filing Date: Tue Jan 08 00:59:59 CET 2013
IPC: G06F 9/455
Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventors: ASAAD, Sameh W.
KAPUR, Mohit
Title: CYCLE ACCURATE AND CYCLE REPRODUCIBLE MEMORY FOR AN FPGA BASED HARDWARE ACCELERATOR
Abstract:
A method, system and computer program product are disclosed for using a Field Programmable Gate Array (FPGA) to simulate operations of a device under test (DUT). The DUT includes a device memory having a number of input ports, and the FPGA is associated with a target memory having a second number of input ports, the second number being less than the first number. In one embodiment, a given set of inputs is applied to the device memory at a frequency Fd and in a defined cycle of time, and the given set of inputs is applied to the target memory at a frequency Ft. Ft is greater than Fd and cycle accuracy is maintained between the device memory and the target memory. In an embodiment, a cycle accurate model of the DUT memory is created by separating the DUT memory interface protocol from the target memory storage array.