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1. (WO2013147898) TRACING MECHANISM FOR RECORDING SHARED MEMORY INTERLEAVINGS ON MULTI-CORE PROCESSORS
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2013/147898 International Application No.: PCT/US2012/031735
Publication Date: 03.10.2013 International Filing Date: 30.03.2012
IPC:
G06F 9/06 (2006.01) ,G06F 9/30 (2006.01) ,G06F 9/38 (2006.01) ,G06F 15/80 (2006.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
9
Arrangements for programme control, e.g. control unit
06
using stored programme, i.e. using internal store of processing equipment to receive and retain programme
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
9
Arrangements for programme control, e.g. control unit
06
using stored programme, i.e. using internal store of processing equipment to receive and retain programme
30
Arrangements for executing machine- instructions, e.g. instruction decode
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
9
Arrangements for programme control, e.g. control unit
06
using stored programme, i.e. using internal store of processing equipment to receive and retain programme
30
Arrangements for executing machine- instructions, e.g. instruction decode
38
Concurrent instruction execution, e.g. pipeline, look ahead
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
15
Digital computers in general; Data processing equipment in general
76
Architectures of general purpose stored programme computers
80
comprising an array of processing units with common control, e.g. single instruction multiple data processors
Applicants: POKAM, Gilles A.[US/US]; US (UsOnly)
PEREIRA, Cristiano L.[US/US]; US (UsOnly)
ADL-TABATABA, Ali-reza[US/US]; US (UsOnly)
INTEL CORPORATION[US/US]; 2200 Mission College Boulevard Santa Clara, California 95052, US (AllExceptUS)
Inventors: POKAM, Gilles A.; US
PEREIRA, Cristiano L.; US
ADL-TABATABA, Ali-reza; US
Agent: ROZMAN, Mark J.; Trop, Pruner & Hu, P.C. 1616 S. Voss Rd., Ste. 750 Houston, Texas 77057-2631, US
Priority Data:
Title (EN) TRACING MECHANISM FOR RECORDING SHARED MEMORY INTERLEAVINGS ON MULTI-CORE PROCESSORS
(FR) MÉCANISME DE TRAÇAGE POUR ENREGISTRER DES ENTRELACEMENTS DE MÉMOIRE PARTAGÉE SUR DES PROCESSEURS MULTICŒURS
Abstract:
(EN) A memory race recorder (MRR) is provided. The MRR includes a multi-core processor having a relaxed memory consistency model, an extension to the multi-core processor, the extension to store chunks, the chunk having a chunk size (CS) and an instruction count (IC), and a plurality of cores to execute instructions. The plurality of cores executes load/store instructions to/from a store buffer (STB) and a simulated memory to store the value when the value is not in the STB. The oldest value in the STB is transferred to the simulated memory when the IC is equal to zero and the CS is greater than zero. The MRR logs a trace entry comprising the CS, the IC, and a global timestamp, the global timestamp proving a total order across all logged chunks.
(FR) L'invention porte sur un enregistreur d'accès mémoire (MRR). Le MRR comprend un processeur multicœur ayant un modèle de cohérence de mémoire relaxé, une extension au processeur multicœur, l'extension servant à stocker des blocs, le bloc ayant une taille de bloc (CS) et un total d'instructions (IC), et une pluralité de cœurs pour exécuter des instructions. La pluralité de cœurs exécutent des instructions de chargement/stockage vers/depuis un tampon de stockage (STB) et une mémoire simulée pour stocker la valeur quand la valeur ne se trouve pas dans le STB. La plus ancienne valeur dans le STB est transférée à la mémoire simulée quand l'IC est égal à zéro et la CS est supérieure à zéro. Le MRR journalise une entrée de trace comprenant la CS, l'IC et une estampille temporelle globale, l'estampille temporelle globale prouvant un ordre total parmi tous les blocs journalisés.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)