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1. WO2013147887 - CONTEXT SWITCHING MECHANISM FOR A PROCESSING CORE HAVING A GENERAL PURPOSE CPU CORE AND A TIGHTLY COUPLED ACCELERATOR

Publication Number WO/2013/147887
Publication Date 03.10.2013
International Application No. PCT/US2012/031681
International Filing Date 30.03.2012
IPC
G06F 9/06 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
G06F 12/10 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
10Address translation
G06F 15/80 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
15Digital computers in general; Data processing equipment in general
76Architectures of general purpose stored program computers
80comprising an array of processing units with common control, e.g. single instruction multiple data processors
CPC
G06F 9/30036
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
30003Arrangements for executing specific machine instructions
30007to perform operations on data operands
30036Instructions to perform operations on packed data, e.g. vector operations
G06F 9/3016
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
30145Instruction analysis, e.g. decoding, instruction word fields
3016Decoding the operand specifier, e.g. specifier format
G06F 9/3851
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
38Concurrent instruction execution, e.g. pipeline, look ahead
3836Instruction issuing, e.g. dynamic instruction scheduling, out of order instruction execution
3851from multiple instruction streams, e.g. multistreaming
G06F 9/3881
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
38Concurrent instruction execution, e.g. pipeline, look ahead
3877using a slave processor, e.g. coprocessor
3879for non-native instruction execution, e.g. executing a command; for Java instruction set
3881Arrangements for communication of instructions and data
G06F 9/461
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
46Multiprogramming arrangements
461Saving or restoring of program or task context
G06F 9/485
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
46Multiprogramming arrangements
48Program initiating; Program switching, e.g. by interrupt
4806Task transfer initiation or dispatching
4843by program, e.g. task dispatcher, supervisor, operating system
485Task life-cycle, e.g. stopping, restarting, resuming execution
Applicants
  • INTEL CORPORATION [US]/[US] (AllExceptUS)
  • RONEN, Ronny [IL]/[IL] (UsOnly)
  • WEISSMANN, Eliezer [IL]/[IL] (UsOnly)
  • VAITHIANATHAN, Karthikeyan Karthik [IN]/[IN] (UsOnly)
  • COHEN, Ehud [IL]/[IL] (UsOnly)
  • GINZBURG, Boris [IL]/[IL] (UsOnly)
Inventors
  • RONEN, Ronny
  • WEISSMANN, Eliezer
  • VAITHIANATHAN, Karthikeyan Karthik
  • COHEN, Ehud
  • GINZBURG, Boris
Agents
  • O'ROURKE, Robert B.
Priority Data
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) CONTEXT SWITCHING MECHANISM FOR A PROCESSING CORE HAVING A GENERAL PURPOSE CPU CORE AND A TIGHTLY COUPLED ACCELERATOR
(FR) MÉCANISME DE COMMUTATION DE CONTEXTE POUR CŒUR DE TRAITEMENT COMPRENANT UN CŒUR DE CPU POLYVALENT ET UN ACCÉLÉRATEUR FORTEMENT COUPLÉ
Abstract
(EN)
An apparatus is described having multiple cores, each core having: a) an accelerator; and, b) a general purpose CPU coupled to the accelerator. The general purpose CPU has functional unit logic circuitry to execute an instruction that returns an amount of storage space to store context information of the accelerator.
(FR)
L'invention porte sur un appareil qui comprend de multiples cœurs, chaque cœur comprenant : a) un accélérateur; et b) une unité centrale (CPU) polyvalente couplée à l'accélérateur. La CPU polyvalente comprend une circuiterie logique d'unité fonctionnelle pour exécuter une instruction qui renvoie une quantité d'espace de stockage pour stocker des informations de contexte de l'accélérateur.
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