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1. (WO2013145736) NONVOLATILE STORAGE DEVICE
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2013/145736 International Application No.: PCT/JP2013/002082
Publication Date: 03.10.2013 International Filing Date: 27.03.2013
IPC:
H01L 27/105 (2006.01) ,H01L 27/10 (2006.01) ,H01L 45/00 (2006.01) ,H01L 49/00 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
105
including field-effect components
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
45
Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
49
Solid state devices not provided for in groups H01L27/-H01L47/99; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
Applicants:
パナソニック株式会社 PANASONIC CORPORATION [JP/JP]; 大阪府門真市大字門真1006番地 1006, Oaza Kadoma, Kadoma-shi, Osaka 5718501, JP
Inventors:
川島 良男 KAWASHIMA, Yoshio; null
早川 幸夫 HAYAKAWA, Yukio; null
三河 巧 MIKAWA, Takumi; null
Agent:
新居 広守 NII, Hiromori; 大阪府大阪市淀川区西中島5丁目3番10号タナカ・イトーピア新大阪ビル6階新居国際特許事務所内 c/o NII Patent Firm, 6F, Tanaka Ito Pia Shin-Osaka Bldg.,3-10, Nishi Nakajima 5-chome, Yodogawa-ku, Osaka-city, Osaka 5320011, JP
Priority Data:
2012-07828529.03.2012JP
Title (EN) NONVOLATILE STORAGE DEVICE
(FR) DISPOSITIF DE MÉMOIRE NON VOLATILE
(JA) 不揮発性記憶装置
Abstract:
(EN) This nonvolatile storage device is provided with: a memory cell array (10) having a plurality of memory cells (11), each of which is configured of a first variable resistance element (141) and a first current control element (142); and a parameter generating circuit (20) having an evaluation cell (21) configured of a second variable resistance element (241), and a second current control element (242) that has voltage characteristics with current density equal to that of the first current control element (142). On the side surface of the second variable resistance element (241), a conductive short-circuiting layer (151) for short-circuiting between the electrodes is provided.
(FR) Le dispositif de mémoire non volatile de l'invention, est équipé : d'une matrice mémoire (10) possédant une pluralité de cellules mémoires (11) configurées par un premier élément de variation de résistance (141) et un premier élément de commande de courant (142) ; et d'un circuit de génération de paramètre (20) qui possède une cellule d'évaluation (21) configurée par un second élément de variation de résistance (241), et un second élément de commande de courant (242) possédant des caractéristiques de tension de même densité de courant que le premier élément de commande de courant (142). Une couche conductrice de court-circuit (151) créant un court-circuit entre des électrodes, est agencée sur une face latérale du second élément de variation de résistance (241).
(JA)  不揮発性記憶装置は、第1の抵抗変化素子(141)と第1の電流制御素子(142)とから構成された複数のメモリセル(11)を有するメモリセルアレイ(10)と、第2の抵抗変化素子(241)と第1の電流制御素子(142)と同じ電流密度の電圧特性を有する第2の電流制御素子(242)とから構成された評価セル(21)を有するパラメータ発生回路(20)とを備え、第2の抵抗変化素子(241)の側面に、電極間を短絡させる導電性短絡層(151)が設けられている。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)