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1. (WO2013145136) TIME TO DIGITAL CONVERTER AND CONTROL METHOD

Pub. No.:    WO/2013/145136    International Application No.:    PCT/JP2012/058008
Publication Date: Fri Oct 04 01:59:59 CEST 2013 International Filing Date: Wed Mar 28 01:59:59 CEST 2012
IPC: H03M 1/12
Applicants: FUJITSU LIMITED
富士通株式会社
CHAIVIPAS, Win
チャイヴィパース ウィン
MATSUDA, Atsushi
松田 篤
Inventors: CHAIVIPAS, Win
チャイヴィパース ウィン
MATSUDA, Atsushi
松田 篤
Title: TIME TO DIGITAL CONVERTER AND CONTROL METHOD
Abstract:
A first switching unit (101) can switch between a first state in which a first clock signal (Signal) input from a first input pin (IN1) is input to a first delay element (C11), and a second state in which an output signal of a second delay element (C2N) is input. A second switching unit (102) can switch between a first state in which a second clock signal (Ref CLK) input from a second input pin (IN2) is input to a second delay element (C21), and a second state in which an output signal of a first delay element (C1N) is input. A controller (701) sets the first and second switching units to the second state after the two clock signals have been incorporated into the first delay elements (C11-C1N) and the second delay elements (C21-C2N) respectively by setting the first and second switching units (101, 102) to the first state. An output unit (OUT) decodes values stored in FFs (710-71N) in the second state and outputs the obtained phase shift.