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1. (WO2013145055) DEBUGGING CONTROL CIRCUIT, METHOD, AND SYSTEM

Pub. No.:    WO/2013/145055    International Application No.:    PCT/JP2012/008050
Publication Date: Fri Oct 04 01:59:59 CEST 2013 International Filing Date: Tue Dec 18 00:59:59 CET 2012
IPC: G06F 11/34
G06F 11/28
G06F 12/02
Applicants: NEC CORPORATION
日本電気株式会社
KOJIMA, Teruhisa
小嶋 輝久
Inventors: KOJIMA, Teruhisa
小嶋 輝久
Title: DEBUGGING CONTROL CIRCUIT, METHOD, AND SYSTEM
Abstract:
A debugging control apparatus (10) according to an embodiment of the present invention includes a list generator (11) that monitors access made to a storage unit (21) by a circuit to be debugged (20) in a plurality of areas and generates a memory list used to determine an access state in each of the plurality of areas, a selector (12) that selects, with reference to the memory list, an area of the storage unit (21) to which an observation signal output from the circuit to be debugged (20) is transferred, and a transfer controller (13) that transfers the observation signal to the area of the storage unit (21) selected by the selector (12). With this configuration, in the structure in which a RAM is shared for usual-operation use and for trace data storage, the debugging control circuit can transfer trace data to an area not used for usual operation without checking memory use allocation.