Some content of this application is unavailable at the moment.
If this situation persist, please contact us atFeedback&Contact
1. (WO2013143289) GAN SUBSTRATE, SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2013/143289 International Application No.: PCT/CN2012/084300
Publication Date: 03.10.2013 International Filing Date: 08.11.2012
IPC:
H01L 29/06 (2006.01) ,H01L 21/20 (2006.01) ,H01L 29/778 (2006.01) ,H01L 21/335 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
06
characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
20
Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
778
with two-dimensional charge carrier gas channel, e.g. HEMT
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
Applicants:
华为技术有限公司 HUAWEI TECHNOLOGIES CO., LTD. [CN/CN]; 中国广东省深圳市 龙岗区坂田华为总部办公楼 Huawei Administration Building, Bantian, Longgang District Shenzhen, Guangdong 518129, CN
Inventors:
张正海 ZHANG, Zhenghai; CN
张宗民 ZHANG, Zongmin; CN
曹伯承 CAO, Bocheng; CN
Agent:
北京同立钧成知识产权代理有限公司 LEADER PATENT & TRADEMARK FIRM; 中国北京市 海淀区西直门北大街32号枫蓝国际A座8F-6 8F-6,Bldg. A,Winland International Center,No. 32 Xizhimen North Street, Haidian District Beijing 100082, CN
Priority Data:
201210086294.528.03.2012CN
Title (EN) GAN SUBSTRATE, SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
(FR) SUBSTRAT DE GAN, DISPOSITIF À SEMI-CONDUCTEUR ET PROCÉDÉ DE FABRICATION DE CEUX-CI.
(ZH) GaN衬底、半导体器件及其制作方法
Abstract:
(EN) Provided are a GaN substrate, a semiconductor device and a manufacturing method thereof. The GaN substrate comprises: a GaN base (401); an AlGaN layer (402), arranged on the GaN base; and a p-type conductive layer (403), arranged on an active area of the AlGaN layer, and used for consuming surface state negative electrons on the AlGaN layer and neutralizing dangling bonds on the AlGaN layer. By forming the p-type conductive layer on the AlGaN layer, the n-type surface state negative electrons on the AlGaN layer can be consumed and the dangling bonds on the section on the AlGaN layer can be neutralized by hole carriers in the p-type conductive layer, so as to prevent the forming of a virtual gate, thereby suppressing the current collapse effect of the semiconductor device manufactured by the GaN substrate, improving the performance of the semiconductor device and improving the reliability thereof.
(FR) L'invention concerne un substrat de GaN, un dispositif à semi-conducteur et un procédé de fabrication de ceux-ci. Le substrat de GaN comprend : une base de GaN (401); une couche d'Algan (402),), agencée sur la base de GaN ; et une couche conductrice de type p (403), disposée sur une zone active de la couche d'Algan, et utilisée pour consommer des électrons d'état de surface négatifs sur la couche d'Algan et neutraliser les liaisons pendantes sur la couche d'Algan. Par la formation de la couche conductrice de type p sur la couche d'Algan, les électrons négatifs d'état de surface de type n sur la couche d'Algan peuvent être consommés et les liaisons pendantes sur la section sur la couche d'Algan peuvent être neutralisées par des supports de trou dans la couche conductrice de type p, de manière à empêcher la formation d'une grille virtuelle, ce qui permet de supprimer l'effet de l'effondrement du courant du dispositif à semi-conducteur fabriqué par le substrat de GaN, améliore la performance du dispositif à semi - conducteur et améliore la fiabilité de celui - ci.
(ZH) 提供了一种GaN衬底、半导体器件及其制作方法,GaN衬底包括:GaN基(401);AlGaN层(402),位于GaN基底上;p型导电层(403),位于AlGaN层的有源区上,用于耗尽AlGaN层上的表面态负电子并中和AlGaN层上的悬挂键。通过在AlGaN层上形成p型导电层,能利用p型导电层中的空穴载流子,耗尽n型的AlGaN层上的表面态负电子,中和AlGaN层上的断面的悬挂键,防止虚栅的形成,从而起到抑制以GaN衬底制作的半导体器件的电流崩塌效应,改善半导体器件的性能,提高其可靠性。
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)