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1. WO2013143032 - SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Publication Number WO/2013/143032
Publication Date 03.10.2013
International Application No. PCT/CN2012/000464
International Filing Date 09.04.2012
IPC
H01L 29/78 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66Types of semiconductor device
68controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76Unipolar devices
772Field-effect transistors
78with field effect produced by an insulated gate
H01L 21/762 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71Manufacture of specific parts of devices defined in group H01L21/7086
76Making of isolation regions between components
762Dielectric regions
CPC
H01L 21/76232
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
76Making of isolation regions between components
762Dielectric regions ; , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
76224using trench refilling with dielectric materials
76232of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
H01L 29/0653
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
02Semiconductor bodies ; ; Multistep manufacturing processes therefor
06characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; ; characterised by the concentration or distribution of impurities within semiconductor regions
0603characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
0642Isolation within the component, i.e. internal isolation
0649Dielectric regions, e.g. SiO2 regions, air gaps
0653adjoining the input or output region of a field-effect device, e.g. the source or drain region
H01L 29/7833
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
66Types of semiconductor device ; ; Multistep manufacturing processes therefor
68controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
76Unipolar devices ; , e.g. field effect transistors
772Field effect transistors
78with field effect produced by an insulated gate
7833with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
Applicants
  • 中国科学院微电子研究所 INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES [CN]/[CN] (AllExceptUS)
  • 尹海洲 YIN, Haizhou [CN]/[US] (UsOnly)
  • 蒋葳 JIANG, Wei [CN]/[CN] (UsOnly)
Inventors
  • 尹海洲 YIN, Haizhou
  • 蒋葳 JIANG, Wei
Agents
  • 中国专利代理(香港)有限公司 CHINA PATENT AGENT (H.K.) LTD.
Priority Data
201210088153.729.03.2012CN
Publication Language Chinese (ZH)
Filing Language Chinese (ZH)
Designated States
Title
(EN) SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
(FR) DISPOSITIF SEMI-CONDUCTEUR ET PROCÉDÉ DE FABRICATION DE CELUI-CI
(ZH) 半导体器件及其制造方法
Abstract
(EN)
A semiconductor device comprises: a first epitaxial layer (2) on a substrate (1); and a second epitaxial layer (3) on the first epitaxial layer (2); a MOSFET formed in an active region of the second epitaxial layer (3); and an inverted T-shaped STI (5), formed in the first epitaxial layer (2) and the second epitaxial layer (3) and enclosing the active region. The double-layer epitaxial layer is selectively etched so as to form the inverted T-shaped STI (5), thereby effectively reducing current leakage of the device while not shrinking the area of the active region, and improving the device reliability.
(FR)
L'invention concerne un dispositif semi-conducteur qui comprend : une première couche épitaxiale (2) sur un substrat (1); et une seconde couche épitaxiale (3) sur la première couche épitaxiale (2); un MOSFET formé dans une région active de la seconde couche épitaxiale (3); et une isolation de tranchée superficielle (STI) en forme de T inversé (5), formée dans la première couche épitaxiale (2) et la seconde couche épitaxiale (3), entourant la région active. La couche épitaxiale à double couche est gravée de manière sélective de façon à former la STI en forme de T inversé (5), réduisant ainsi de manière efficace la fuite de courant du dispositif tout en ne diminuant pas l'aire de la région active, et améliorant la fiabilité du dispositif.
(ZH)
一种半导体器件,包括:在衬底(1)上的第一外延层(2);在第一外延层(2)上的第二外延层(3),在第二外延层(3)的有源区中形成MOSFET;反T型的STI(5),形成在第一外延层(2)和第二外延层(3)中,并且包围有源区。采用选择性刻蚀双层外延层从而形成反T型的STI(5),有效减少器件泄漏电流而同时又不会缩小有源区面积,提高了器件的可靠性。
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