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1. (WO2013137860) DYNAMICALLY COMPUTING AN ELECTRICAL DESIGN POINT (EDP) FOR A MULTICORE PROCESSOR
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2013/137860 International Application No.: PCT/US2012/028876
Publication Date: 19.09.2013 International Filing Date: 13.03.2012
IPC:
G06F 1/26 (2006.01) ,G06F 1/32 (2006.01) ,G06F 15/80 (2006.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
1
Details not covered by groups G06F3/-G06F13/82
26
Power supply means, e.g. regulation thereof
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
1
Details not covered by groups G06F3/-G06F13/82
26
Power supply means, e.g. regulation thereof
32
Means for saving power
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
15
Digital computers in general; Data processing equipment in general
76
Architectures of general purpose stored programme computers
80
comprising an array of processing units with common control, e.g. single instruction multiple data processors
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95052, US (AllExceptUS)
BHANDARU, Malini K. [US/US]; US (UsOnly)
DEHAEMER, Eric J. [US/US]; US (UsOnly)
SHRALL, Jeremy J. [US/US]; US (UsOnly)
Inventors:
BHANDARU, Malini K.; US
DEHAEMER, Eric J.; US
SHRALL, Jeremy J.; US
Agent:
ROZMAN, Mark J.; Trop, Pruner & Hu, P.C. 1616 S. Voss Rd., Ste. 750 Houston, Texas 77057-2631, US
Priority Data:
Title (EN) DYNAMICALLY COMPUTING AN ELECTRICAL DESIGN POINT (EDP) FOR A MULTICORE PROCESSOR
(FR) CALCUL DYNAMIQUE D'UN POINT DE CONCEPTION ÉLECTRIQUE (EDP) POUR UN PROCESSEUR MULTINOYAU
Abstract:
(EN) In one embodiment, a multicore processor includes a controller to dynamically limit a maximum permitted turbo mode frequency of its cores based on a core activity pattern of the cores and power consumption information of a unit power table. In one embodiment, the core activity pattern can indicate, for each core, an activity level and a logic unit state of the corresponding core. Further, the unit power table can be dynamically computed based on a temperature of the processor. Other embodiments are described and claimed.
(FR) Dans un mode de réalisation, un processeur multinoyau comprend un contrôleur pour limiter dynamiquement une fréquence de mode turbo maximum autorisée de ses noyaux sur la base d'un modèle d'activité de noyau des noyaux et d'informations de consommation d'énergie d'une table de puissance d'unité. Dans un mode de réalisation, le modèle d'activité de noyau peut indiquer, pour chaque noyau, un niveau d'activité et un état d'unité logique du noyau correspondant. En outre, la table de puissance d'unité peut être calculée dynamiquement sur la base d'une température du processeur. D'autres modes de réalisation sont décrits et revendiqués.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
US20140195829