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1. (WO2013126018) A METHOD FOR PLATING A COMPONENT
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2013/126018 International Application No.: PCT/SG2013/000073
Publication Date: 29.08.2013 International Filing Date: 22.02.2013
Chapter 2 Demand Filed: 20.12.2013
IPC:
C25D 5/02 (2006.01) ,G03F 7/00 (2006.01) ,H01L 21/3213 (2006.01) ,H01L 23/495 (2006.01) ,H01L 23/525 (2006.01)
C CHEMISTRY; METALLURGY
25
ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
D
PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; JOINING WORKPIECES BY ELECTROLYSIS; APPARATUS THEREFOR
5
Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
02
Electroplating of selected surface areas
G PHYSICS
03
PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
F
PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
7
Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
3205
Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layers; After-treatment of these layers
321
After-treatment
3213
Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
488
consisting of soldered or bonded constructions
495
Lead-frames
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
522
including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
525
with adaptable interconnections
Applicants:
ROKKO LEADFRAMES PTE LTD [SG/SG]; 61 Kaki Bukit Road 2 Singapore 417869, SG
Inventors:
SINGH, Paramgeet; SG
YARANIAN, Ravi; SG
Agent:
ENGLISH, Matthew; Marks & Clerk Singapore LLP Tanjong Pagar PO Box 636 Singapore 910816, SG
Priority Data:
201201382-724.02.2012SG
Title (EN) A METHOD FOR PLATING A COMPONENT
(FR) PROCÉDÉ DE PLACAGE D'UN COMPOSANT
Abstract:
(EN) A method for selectively plating a connector pin, the method comprising the steps of: providing said connector pin; applying a layer of a barrier metal to said connector pin; applying a photo-resist material to said connector pin, then; selectively exposing a portion of the photo-resist material so as to impart a pattern on the exposed portion; removing unexposed photo-resist material; applying a layer of precious metal to the connector pin such that said precious metal layer is applied to the exposed portion only.
(FR) L'invention concerne un procédé de plaquage sélectif d'une broche de connecteur. Le procédé comprend les étapes suivante : fourniture de ladite broche de connecteur; application d'une couche de métal barrière sur ladite broche de connecteur; application d'une pellicule photorésistante à ladite broche de connecteur, puis; exposition, de façon sélective, d'une partie de la pellicule photorésistante de manière à transférer un motif sur la partie exposée; élimination de la pellicule photorésistante non exposée; application d'une couche de métal précieux sur la broche de connecteur de telle sorte que ladite couche de métal précieux ne soit appliquée que sur la partie exposée.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)