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1. (WO2013125014) SEMICONDUCTOR DEVICE MANUFACTURING METHOD
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2013/125014 International Application No.: PCT/JP2012/054434
Publication Date: 29.08.2013 International Filing Date: 23.02.2012
IPC:
H01L 21/324 (2006.01) ,C30B 29/06 (2006.01) ,C30B 33/02 (2006.01) ,H01L 21/22 (2006.01) ,H01L 21/336 (2006.01) ,H01L 29/739 (2006.01) ,H01L 29/78 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
324
Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
C CHEMISTRY; METALLURGY
30
CRYSTAL GROWTH
B
SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
29
Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
02
Elements
06
Silicon
C CHEMISTRY; METALLURGY
30
CRYSTAL GROWTH
B
SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
33
After-treatment of single crystals or homogeneous polycrystalline material with defined structure
02
Heat treatment
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
22
Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regions; Redistribution of impurity materials, e.g. without introduction or removal of further dopant
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
70
Bipolar devices
72
Transistor-type devices, i.e. able to continuously respond to applied control signals
739
controlled by field effect
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
Applicants: NAKAZAWA, Haruo[JP/JP]; JP (UsOnly)
OGINO, Masaaki[JP/JP]; JP (UsOnly)
KURIBAYASHI, Hidenao[JP/JP]; JP (UsOnly)
TERANISHI, Hideaki[JP/JP]; JP (UsOnly)
FUJI ELECTRIC CO., LTD.[JP/JP]; 1-1, Tanabeshinden, Kawasaki-ku, Kawasaki-shi, Kanagawa 2109530, JP (AllExceptUS)
Inventors: NAKAZAWA, Haruo; JP
OGINO, Masaaki; JP
KURIBAYASHI, Hidenao; JP
TERANISHI, Hideaki; JP
Agent: SAKAI, Akinori; A. SAKAI & ASSOCIATES, 20F, Kasumigaseki Building, 2-5, Kasumigaseki 3-chome, Chiyoda-ku, Tokyo 1006020, JP
Priority Data:
Title (EN) SEMICONDUCTOR DEVICE MANUFACTURING METHOD
(FR) PROCÉDÉ DE FABRICATION DE DISPOSITIF À SEMI-CONDUCTEUR
(JA) 半導体装置の製造方法
Abstract:
(EN) In the present invention, a reverse blocking IGBT is manufactured using a silicon wafer cut from a single crystal silicon ingot manufactured by means of a floating method using, as a raw material, a single crystal silicon ingot that is manufactured by means of the Czochralski method. An isolating layer to be formed for the purpose of ensuring the reverse blocking performance of the reverse blocking IGBT is formed by diffusing an impurity by thermal diffusion, said impurity having been introduced into the silicon wafer. The thermal diffusion for forming the isolating layer is performed in an inert gas atmosphere at 1,290°C or higher but lower than the melting point of silicon. Consequently, crystal defects are not generated in the silicon wafer, and reverse withstand voltage failures and forward direction failures are prevented from being generated in the reverse blocking IGBT, thereby improving the yield rate of the semiconductor element.
(FR) Selon la présente invention, un transistor bipolaire à porte isolée de blocage inverse est fabriqué à l'aide d'une tranche de silicium qui est découpée à partir d'un lingot de silicium monocristallin et qui est fabriquée au moyen d'un procédé flottant à l'aide, en tant que matière première, d'un lingot de silicium monocristallin qui est fabriqué au moyen d'un procédé de Czochralski. Une couche isolante devant être formée afin de garantir la performance de blocage inverse du transistor bipolaire à porte isolée de blocage inverse est formée en diffusant une impureté par diffusion thermique, ladite impureté ayant été introduite dans la tranche de silicium. La diffusion thermique permettant de former la couche isolante est mise en œuvre dans une atmosphère de gaz inerte à une température supérieure ou égale à 1 290 °C mais inférieure au point de fusion du silicium. Par conséquent, aucun défaut cristallin n'est généré dans la tranche de silicium, et il est possible d'empêcher la génération de pannes de tension de tenue inverse et de pannes en sens direct dans le transistor bipolaire à porte isolée de blocage inverse, ce qui permet d'améliorer le taux de rendement de l'élément semi-conducteur.
(JA)  チョクラルスキー法で作製された単結晶シリコンインゴットを原料としてフローティング法で作製された単結晶シリコンインゴットから切断されたシリコンウエハを用いて、逆阻止型IGBTを作製する。逆阻止型IGBTの逆阻止能力を確保するために形成される分離層は、シリコンウエハに導入された不純物を熱拡散処理によって拡散させることで形成される。分離層を形成する熱拡散処理は、不活性ガス雰囲気中で、1290℃以上、シリコンの融点未満の温度で行われる。これにより、シリコンウエハに結晶欠陥が発生せず、逆阻止型IGBTに逆耐圧不良や順方向不良が発生することを防止することができ、半導体素子の良品率を向上させることができる。
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)