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1. (WO2013123679) DIFFUSION BLOCKING LAYER, METAL INTERCONNECTED STRUCTURE AND MANUFACTURING PROCESS THEREFOR
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2013/123679 International Application No.: PCT/CN2012/071761
Publication Date: 29.08.2013 International Filing Date: 29.02.2012
IPC:
H01L 21/768 (2006.01) ,H01L 21/31 (2006.01) ,H01L 23/535 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
768
Applying interconnections to be used for carrying current between separate components within a device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
535
including internal interconnections, e.g. cross-under constructions
Applicants:
马小龙 MA, Xiaolong [CN/CN]; CN (UsOnly)
殷华湘 YIN, Huaxiang [CN/CN]; CN (UsOnly)
赵利川 ZHAO, Lichuan [CN/CN]; CN (UsOnly)
中国科学院微电子研究所 INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES [CN/CN]; 中国北京市 朝阳区北土城西路3号 No. 3 Beitucheng West Road, Chaoyang District Beijing 100029, CN (AllExceptUS)
Inventors:
马小龙 MA, Xiaolong; CN
殷华湘 YIN, Huaxiang; CN
赵利川 ZHAO, Lichuan; CN
Agent:
中科专利商标代理有限责任公司 CHINA SCIENCE PATENT AND TRADEMARK AGENT LTD.; 中国北京市海淀区西三环北路87号国际财经中心D座11层 11/F., Bldg. D, International Finance and Economics Center No.87, West 3rd Ring North Rd., Haidian District Beijing 100089, CN
Priority Data:
201210044177.224.02.2012CN
Title (EN) DIFFUSION BLOCKING LAYER, METAL INTERCONNECTED STRUCTURE AND MANUFACTURING PROCESS THEREFOR
(FR) COUCHE D'ARRÊT DE DIFFUSION, STRUCTURE INTERCONNECTÉE MÉTALLIQUE ET LEUR PROCESSUS DE FABRICATION
(ZH) 扩散阻挡层、金属互连结构及其制造方法
Abstract:
(EN) Provided are a diffusion blocking layer, a metal interconnected structure and a manufacturing process therefor. The process comprises: successively forming, in a semiconductor structure (10), a first interconnected layer (20), a second interconnected layer (30), and a third interconnected layer (40), wherein the first interconnected layer (20) includes a first diffusion blocking layer (202), the second interconnected layer (30) includes a second diffusion blocking layer (302), and the third interconnected layer (40) includes a third diffusion blocking layer (402); patterning two adjacent interconnected layers by a dual Damascene process to form grooves and filling them with an electrically conductive material to form electrically conductive structures (210, 308, 410), whereby electrically conductive blocking layers (208, 306, 408) are formed on the sides and bottom face of the grooves; diffusion blocking layers (202, 302, 402) are provided on at least a part of the surface of the electrically conductive structures (210, 308, 410); the diffusion blocking layers (202, 302, 402) comprise insulated amorphous carbon.
(FR) La présente invention a trait à une couche d'arrêt de diffusion, à une structure interconnectée métallique et à leur processus de fabrication. Le processus comprend les étapes consistant : à former successivement, dans une structure semi-conductrice (10), une première couche interconnectée (20), une deuxième couche interconnectée (30) et une troisième couche interconnectée (40), laquelle première couche interconnectée (20) inclut une première couche d'arrêt de diffusion (202), laquelle deuxième couche interconnectée (30) inclut une deuxième couche d'arrêt de diffusion (302) et laquelle troisième couche interconnectée (40) inclut une troisième couche d'arrêt de diffusion (402) ; à former des motifs sur deux couches interconnectées adjacentes au moyen d'un processus de damasquinage double en vue de former des rainures et de les remplir avec un matériau électroconducteur afin de former des structures électroconductrices (210, 308, 410), grâce à quoi des couches d'arrêt électroconductrices (208, 306, 408) sont formées sur les côtés et la face inférieure des rainures ; les couches d'arrêt de diffusion (202, 302, 402) étant prévues sur au moins une partie de la surface des structures électroconductrices (210, 308, 410) ; les couches d'arrêt de diffusion (202, 302, 402) comprenant du carbone amorphe isolé.
(ZH) 提供一种扩散阻挡层、金属互连结构及其制造方法。该方法包括:在半导体结构(10)依次形成第一互连层(20)、第二互连层(30)和第三互连层(40);其中第一互连层(20)中包括第一扩散阻挡层(202),第二互连层(30)中包括第二扩散阻挡层(302),在第三互连层(40)中包括第三扩散阻挡层(402);通过双大马士革工艺对两层相邻互连层进行构图形成沟槽并填充导电材料形成导电结构(210,308,410);其中在沟槽中的侧面和底面上形成导电阻挡层(208,306,408);在导电结构(210,308,410)至少一部分表面上设置扩散阻挡层(202,302,402);所述扩散阻挡层(202,302,402)包括绝缘非晶碳。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)