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Machine translation
1. (WO2013119643) MULTILAYER ELECTRONICS ASSEMBLY AND METHOD FOR EMBEDDING ELECTRICAL CIRCUIT COMPONENTS WITHIN A THREE DIMENSIONAL MODULE
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2013/119643    International Application No.:    PCT/US2013/024907
Publication Date: 15.08.2013 International Filing Date: 06.02.2013
IPC:
H05K 3/46 (2006.01), H05K 1/18 (2006.01), H01L 23/12 (2006.01)
Applicants: CRANE ELECTRONICS, INC. [US/US]; 10201 Willows Road Redmond, Washington 98052 (US)
Inventors: PARKER, Ernest, Clyde; (US).
LAURIELLO, Philip, Joseph; (US)
Agent: BULLARD, Christopher, A.; Seed Intellectual Property Law Group PLLC Suite 5400 701 Fifth Avenue Seattle, Washington 98104-7064 (US)
Priority Data:
61/596,652 08.02.2012 US
13/758,843 04.02.2013 US
Title (EN) MULTILAYER ELECTRONICS ASSEMBLY AND METHOD FOR EMBEDDING ELECTRICAL CIRCUIT COMPONENTS WITHIN A THREE DIMENSIONAL MODULE
(FR) ENSEMBLE ÉLECTRONIQUE MULTICOUCHE ET PROCÉDÉ PERMETTANT D'INTÉGRER DES COMPOSANTS DE CIRCUIT ÉLECTRIQUE DANS UN MODULE TRIDIMENSIONNEL
Abstract: front page image
(EN)A multilayer electronics assembly and associated method of manufacture are provided. The multilayer electronics assembly includes a plurality of stacked substrate layers. Each of the substrate layers is fusion bonded to at least an adjacent one of the plurality of substrate layers. A first discrete electrical circuit component is bonded to a first layer of the plurality of layers. A bonding material is interposed between the discrete electrical circuit component and the first layer. The bonding material has a reflow temperature at which the bonding material becomes flowable that is higher than a fusion bonding temperature of the substrate layers.
(FR)L'invention concerne un ensemble électronique multicouche et un procédé de fabrication associé. L'ensemble électronique multicouche comporte une pluralité de couches de substrat empilées. Chacune des couches de substrat est liée par fusion à au moins une couche de substrat adjacente de la pluralité de couches de substrat. Un premier composant discret de circuit électrique est relié à une première couche de la pluralité de couches. Un matériau de liaison est interposé entre le composant discret de circuit électrique et la première couche. Le matériau de liaison présente une température de refusion, à laquelle le matériau de liaison devient coulant, supérieure à une température de liaison par fusion des couches de substrat.
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)