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1. (WO2013118959) HIGH-VOLTAGE INTEGRATED CIRCUIT
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2013/118959    International Application No.:    PCT/KR2012/009626
Publication Date: 15.08.2013 International Filing Date: 15.11.2012
IPC:
G05F 3/02 (2006.01), G05F 3/24 (2006.01)
Applicants: TAEJIN TECHNOLOGY CO., LTD. [KR/KR]; 205 Radio Engineering Center 694 Tamnip-dong Yuseong-gu Daejeon 305-510 (KR)
Inventors: PARK, Hyun; (KR).
CHANG, Keeseok; (KR)
Agent: JEONG, Hwoihwan; 501 KT&G Bd., 926 Dunsan-dong, Seo-gu Daejeon 302-120 (KR)
Priority Data:
10-2012-0013040 09.02.2012 KR
Title (EN) HIGH-VOLTAGE INTEGRATED CIRCUIT
(FR) CIRCUIT INTÉGRÉ À HAUTE TENSION
(KO) 고전압 집적회로
Abstract: front page image
(EN)The present invention relates to a high-voltage integrated circuit, including: a high-voltage enable signal generating unit for generating a high-voltage enable signal (VENHB) by dividing an input voltage (VIN) via a resistor (R2), which controls a bias current, and a voltage-dropping unit, when an external enable signal (Ext EN) turns on an n-type MOS transistor (NM1); and a low-voltage enable signal generating unit for generating a low-voltage enable signal (VENL) by driving a buffer unit using a voltage limited by a Zener diode via a resistor (R5), which controls a bias current, and a first current mirror, when the external enable signal (Ext EN) turns on an n-type MOS transistor (NM2).
(FR)La présente invention concerne un circuit intégré à haute tension qui comprend : une unité de génération d'un signal de validation à haute tension, qui permet de générer un signal de validation à haute tension (VENHB) en divisant une tension d'entrée (VIN) à l'aide d'une résistance (R2) qui commande un courant de polarisation, et une unité d'abaissement de tension, lorsqu'un signal de validation externe (Ext EN) rend passant un transistor MOS de type n (NM1); une unité de génération de signal de validation à basse tension qui permet de générer un signal de validation à basse tension (VENL) en attaquant une unité de tampon à l'aide d'une tension limitée par une diode Zener, par l'intermédiaire d'une résistance (R5) qui commande un courant de polarisation, et un premier miroir de courant, lorsque le signal de validation externe (Ext EN) rend passant un transistor MOS de type n (NM2).
(KO)본 발명은 고전압 집적회로에 관한 것으로, 외부 이네이블 신호(Ext EN)가 n형 모스트랜지스터(NM1)를 턴온하면, 바이어스 전류 조절을 위한 저항(R2)을 통해 입력전압(VIN)을 전압 강하부에 의해 고전압 이네이블 신호(VENHB)를 생성하는 고전압 이네이블 신호 생성부 및 상기 외부 이네이블 신호(Ext EN)가 n형 모스트랜지스터(NM2)를 턴온하면, 바이어스 전류 조절을 위한 저항(R5)과 제1 전류미러를 통해 제너다이오드에 의해 제한된 전압이 버퍼부를 구동하여 저전압 이네이블 신호(VENL)를 생성하는 저전압 이네이블 신호 생성부를 포함하는 것을 특징으로 한다.
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: Korean (KO)
Filing Language: Korean (KO)