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1. (WO2013118449) METHOD OF DRIVING NONVOLATILE SEMICONDUCTOR DEVICE
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2013/118449 International Application No.: PCT/JP2013/000426
Publication Date: 15.08.2013 International Filing Date: 28.01.2013
IPC:
H01L 21/8246 (2006.01) ,G11C 11/22 (2006.01) ,H01L 21/336 (2006.01) ,H01L 27/105 (2006.01) ,H01L 29/788 (2006.01) ,H01L 29/792 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8232
Field-effect technology
8234
MIS technology
8239
Memory structures
8246
Read-only memory structures (ROM)
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
11
Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21
using electric elements
22
using ferroelectric elements
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
105
including field-effect components
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
788
with floating gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
792
with charge trapping gate insulator, e.g. MNOS-memory transistor
Applicants: PANASONIC CORPORATION[JP/JP]; 1006, Oaza Kadoma, Kadoma-shi, Osaka 5718501, JP
Inventors: KANEKO, Yukihiro; null
Agent: OKUDA, Seiji; OKUDA & ASSOCIATES, 10th Floor, Osaka Securities Exchange Bldg., 8-16, Kitahama 1-chome, Chuo-ku, Osaka-shi, Osaka 5410041, JP
Priority Data:
2012-02360307.02.2012JP
Title (EN) METHOD OF DRIVING NONVOLATILE SEMICONDUCTOR DEVICE
(FR) PROCÉDÉ DE COMMANDE D'UN DISPOSITIF SEMI-CONDUCTEUR NON VOLATILE
(JA) 不揮発性半導体装置を駆動する方法
Abstract:
(EN) In the present invention, pulse voltages (V1, V2) are applied to a first upper gate electrode (17a) and a second upper gate electrode (17b) respectively for a period of time shorter than the period necessary to invert all polarization existing within a ferroelectric film (13), while applying voltages (Vs, Vd, V3) to a source electrode (15), a drain electrode (16), and a lower gate electrode film (12) respectively, so that widths (WRH1, WRH2) become wider and a width (WRL) becomes narrower. The pulse voltages (V1, V2) are lower than the voltage necessary to invert all the polarization existing within the ferroelectric film (13). The voltages (Vs, Vd, V3) and the pulse voltages (V1, V2) satisfy the relationship of Vs, Vd, V3 < V1, V2.
(FR) Dans la présente invention, des tensions (V1, V2) d'impulsion sont appliquées respectivement à une première électrode de grille supérieure (17a) et à une seconde électrode de grille supérieure (17b), pour une durée plus courte que la période nécessaire pour inverser toute polarisation existante à l'intérieur d'un film ferroélectrique (13), tout en appliquant des tensions (Vs, Vd, V3) respectivement à une électrode de source (15), à une électrode (16) de drain, et à un film d'électrode de grille inférieure (12), de sorte que les largeurs (WRH1, WRH2) deviennent plus larges, et qu'une largeur (WRL) devient plus étroite. Les tensions (V1, V2) d'impulsion sont inférieures à la tension nécessaire pour inverser toute polarisation existante à l'intérieur du film ferroélectrique (13). Les tensions (Vs, Vd, V3) et les tensions (V1, V2) d'impulsion satisfont à la relation selon laquelle Vs , Vd , V3 < V1 , V2.
(JA)  幅WRH1および幅WRH2が大きくなり、幅WRLが小さくなるように、電圧Vs、Vd、およびV3が、それぞれ、ソース電極(15)、ドレイン電極(16)、および下部ゲート電極膜(12)に印加されながら、強誘電体膜(13)に含まれる全ての分極を反転させるのに必要な期間よりも短い期間の間、パルス電圧V1およびV2が、それぞれ、第1上部ゲート電極(17a)および第2上部ゲート電極(17b)に印加される。パルス電圧V1およびV2は、強誘電体膜(13)に含まれる全ての分極を反転させるために必要な電圧よりも小さい。電圧Vs、VdおよびV3ならびにパルス電圧V1およびV2は、Vs,Vd,V3<V1,V2の関係を充足する。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)