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1. (WO2013118229) WIRING CIRCUIT, WIRING BOARD, AND METHOD FOR MANUFACTURING WIRING BOARD
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2013/118229 International Application No.: PCT/JP2012/008313
Publication Date: 15.08.2013 International Filing Date: 26.12.2012
IPC:
H05K 3/46 (2006.01) ,H05K 1/11 (2006.01) ,H05K 3/40 (2006.01)
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3
Apparatus or processes for manufacturing printed circuits
46
Manufacturing multi-layer circuits
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
1
Printed circuits
02
Details
11
Printed elements for providing electric connections to or between printed circuits
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3
Apparatus or processes for manufacturing printed circuits
40
Forming printed elements for providing electric connections to or between printed circuits
Applicants:
永野 琢 NAGANO, Taku [JP/JP]; JP (US)
吉田 貴大 YOSHIDA, Takahiro [JP/JP]; JP (US)
柳田 伸行 YANAGIDA, Nobuyuki [JP/JP]; JP (US)
太陽インキ製造株式会社 TAIYO INK MFG. CO., LTD. [JP/JP]; 埼玉県比企郡嵐山町大字平澤900番地 900, Oaza Hirasawa, Ranzan-machi, Hiki-gun, Saitama 3550215, JP (AllExceptUS)
Inventors:
永野 琢 NAGANO, Taku; JP
吉田 貴大 YOSHIDA, Takahiro; JP
柳田 伸行 YANAGIDA, Nobuyuki; JP
Agent:
特許業務法人 天城国際特許事務所 AMAGI INTERNATIONAL PATENT LAW OFFICE; 神奈川県川崎市幸区堀川町580番地 ソリッドスクエア 東館4階 SOLID SQUARE EAST TOWER 4F, 580, Horikawa-cho, Saiwai-ku, Kawasaki-shi, Kanagawa 2120013, JP
Priority Data:
2012-02738210.02.2012JP
Title (EN) WIRING CIRCUIT, WIRING BOARD, AND METHOD FOR MANUFACTURING WIRING BOARD
(FR) CIRCUIT DE CÂBLAGE, CARTE DE CÂBLAGE ET PROCÉDÉ DE FABRICATION DE CARTE DE CÂBLAGE
(JA) 配線回路、配線基板及び配線基板の製造方法
Abstract:
(EN) Provided are a wiring circuit wherein a first electrode layer and a second electrode layer are stably electrically connected to each other, said first electrode layer and second electrode layer being formed by having therebetween a via hole formed in an insulating layer, and a method for forming the circuit. A wiring circuit of the embodiment of the present invention is characterized in that the via hole has, in the via hole, a hole that reaches the first electrode layer.
(FR) L'invention porte sur un circuit de câblage dans lequel une première couche d'électrode et une seconde couche d'électrode sont électriquement connectées l'une à l'autre d'une manière stable, ladite première couche d'électrode et ladite seconde couche d'électrode étant formées en comportant entre elles un trou d'interconnexion formé dans une couche isolante, et sur un procédé pour former le circuit. Un circuit de câblage selon le mode de réalisation de la présente invention est caractérisé en ce que le trou d'interconnexion comprend, dans le trou d'interconnexion, un trou qui atteint la première couche d'électrode.
(JA)  絶縁層に形成したビアホールを介して形成される第一の電極層と第二の電極層を安定に導通させる配線回路及びその回路形成方法を提供する。 本実施形態に係る配線回路は、上記ビアホールがビアホール内に上記第一の電極層に達する穴部を有することを特徴とする。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)