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1. (WO2013118203) SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2013/118203 International Application No.: PCT/JP2012/005716
Publication Date: 15.08.2013 International Filing Date: 10.09.2012
IPC:
H01L 29/78 (2006.01) ,H01L 21/336 (2006.01) ,H01L 29/12 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
12
characterised by the materials of which they are formed
Applicants:
工藤 千秋 KUDOU, Chiaki; null (UsOnly)
清澤 努 KIYOSAWA, Tsutomu; null (UsOnly)
パナソニック株式会社 PANASONIC CORPORATION [JP/JP]; 大阪府門真市大字門真1006番地 1006, Oaza Kadoma, Kadoma-shi, Osaka 5718501, JP (AllExceptUS)
Inventors:
工藤 千秋 KUDOU, Chiaki; null
清澤 努 KIYOSAWA, Tsutomu; null
Agent:
特許業務法人前田特許事務所 MAEDA & PARTNERS; 大阪府大阪市中央区本町2丁目5番7号 大阪丸紅ビル5階 Osaka-Marubeni Bldg.5F, 5-7,Hommachi 2-chome, Chuo-ku, Osaka-shi, Osaka 5410053, JP
Priority Data:
2012-02707410.02.2012JP
Title (EN) SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
(FR) DISPOSITIF SEMI-CONDUCTEUR ET SON PROCÉDÉ DE FABRICATION
(JA) 半導体装置及びその製造方法
Abstract:
(EN) A first first-conductivity-type impurity region (4) is provided at an upper part of a semiconductor layer (102) positioned at the periphery of a trench (12). A gate electrode (8) is provided, with a gate insulating film (11) therebetween, on the side wall surfaces of the trench (12) and on the semiconductor layer (102) positioned at the periphery of the trench (12). Between the gate electrode (8) positioned at the periphery of the trench (12), and the first first-conductivity-type impurity region (4), a second-conductivity-type impurity region (50) and a second first-conductivity-type impurity region (51) are sequentially provided from the side of the first first-conductivity-type impurity region (4).
(FR) Selon l'invention, une première région d'impureté d'un premier type de conductivité (4) est disposée sur une partie supérieure d'une couche de semi-conducteur (102) positionnée à la périphérie d'une tranchée (12). Une électrode de grille (8) est disposée, un film isolant de grille (11) étant entre celles-ci, sur les surfaces de paroi latérales de la tranchée (12) et sur la couche de semi-conducteur (102) positionnée à la périphérie de la tranchée (12). Entre l'électrode de grille (8) positionnée à la périphérie de la tranchée (12), et la première région d'impureté du premier type de conductivité (4), une région d'impureté d'un second type de conductivité (50) et une seconde région d'impureté du premier type de conductivité (51) sont disposées de manière séquentielle à partir du côté de la première région d'impureté du premier type de conductivité (4).
(JA)  トレンチ(12)の周囲に位置する半導体層(102)の上部に第1の第一導電型不純物領域(4)が設けられている。トレンチ(12)の側壁面の上、及びトレンチ(12)の周囲に位置する半導体層(102)の上に、ゲート絶縁膜(11)を挟んでゲート電極(8)が設けられている。トレンチ(12)の周囲に位置するゲート電極(8)と第1の第一導電型不純物領域(4)との間に、第1の第一導電型不純物領域(4)側から第二導電型不純物領域(50)と第2の第一導電型不純物領域(51)とが介在している。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)