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1. (WO2013117077) TRENCH FIELD-EFFECT TRANSISTOR AND PREPARATION METHOD THEREFOR
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2013/117077 International Application No.: PCT/CN2012/078793
Publication Date: 15.08.2013 International Filing Date: 18.07.2012
IPC:
H01L 21/336 (2006.01) ,H01L 29/78 (2006.01) ,H01L 21/28 (2006.01) ,H01L 29/423 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
28
Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/268158
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40
Electrodes
41
characterised by their shape, relative sizes or dispositions
423
not carrying the current to be rectified, amplified or switched
Applicants: ZHOU, Hongwei[CN/CN]; CN (UsOnly)
GAO, Dongyue[CN/CN]; CN (UsOnly)
CSMC TECHNOLOGIES FAB1 CO., LTD[CN/CN]; No.5 Hanjiang Road, Wuxi New District Wuxi, Jiangsu 214028, CN (AllExceptUS)
Inventors: ZHOU, Hongwei; CN
GAO, Dongyue; CN
Agent: CHINA PATENT AGENT (HK) LTD.; 22/F., Great Eagle Center 23 Harbour Road Hong Kong, CN
Priority Data:
201210030159.910.02.2012CN
Title (EN) TRENCH FIELD-EFFECT TRANSISTOR AND PREPARATION METHOD THEREFOR
(FR) TRANSISTOR À EFFET DE CHAMP À TRANCHÉE ET SON PROCÉDÉ DE PRÉPARATION
(ZH) 一种沟槽场效应器件及其制备方法
Abstract:
(EN) Disclosed are a trench field-effect transistor and a preparation method therefor. The preparation method comprises: providing a substrate, the substrate comprising an epitaxial layer which is formed on a semiconductor substrate of the substrate and a trench which is formed in the epitaxial layer; forming a sacrificial dielectric layer on the bottom and the side wall of the trench; forming a heavily-doped polysilicon region at the bottom of the trench, removing a part of the sacrificial dielectric layer which is not covered by the heavily-doped polysilicon region to expose the epitaxial layer of the side wall of the trench; and simultaneously oxidizing the heavily-doped polysilicon region and the epitaxial layer of the side wall of the trench, to synchronously form a thick oxide layer and a trench side-wall gate dielectric layer respectively on the bottom and the side wall of the trench. The thickness of the thick oxide layer is greater than that of the trench side-wall gate dielectric layer which is synchronously formed together with the thick oxide layer, and the thick oxide layer is used as the trench bottom gate dielectric layer of the trench field-effect transistor. The preparation method is simple, and the figure of merit for preparing the formed trench field-effect transistor is greatly reduced.
(FR) La présente invention concerne un transistor à effet de champ à tranchée et son procédé de préparation. Le procédé de préparation comprend : la fourniture d'un substrat, le substrat comprenant une couche épitaxiale qui est formée sur un substrat semi-conducteur du substrat et une tranchée qui est formée dans la couche épitaxiale ; la formation d'une couche diélectrique sacrificielle sur le fond et la paroi latérale de la tranchée ; la formation d'une région de silicium polycristallin fortement dopé au fond de la tranchée, en éliminant une partie de la couche diélectrique sacrificielle qui n'est pas recouverte par la région de silicium polycristallin fortement dopé afin de mettre à nu la couche épitaxiale de la paroi latérale de la tranchée ; et l'oxydation simultanée de la région de silicium polycristallin fortement dopé et de la couche épitaxiale de la paroi latérale de la tranchée, afin de former de manière synchrone une couche d'oxyde épaisse et une couche diélectrique de grille de paroi latérale de tranchée sur le fond et la paroi latérale de la tranchée respectivement. L'épaisseur de la couche d'oxyde épaisse est supérieure à celle de la couche diélectrique de grille de paroi latérale de tranchée qui est formée de manière synchrone conjointement avec la couche d'oxyde épaisse, et la couche d'oxyde épaisse est utilisée comme couche diélectrique de grille de fond de tranchée du transistor à effet de champ à tranchée. Le procédé de préparation est simple, et le facteur de mérite pour la préparation dudit transistor à effet de champ à tranchée formé est considérablement réduit.
(ZH) 本发明公开了一种沟槽场效应器件及其制备方法,该制备方法包括:提供基片,该基片包括形成在基片的半导体衬底之上的外延层以及形成于所述外延层中的沟槽;在所述沟槽底部和侧壁形成牺牲介质层;在所述沟槽底部形成重掺杂型多晶硅区域,并去除未被所述重掺杂型多晶硅区域覆盖的部分所述牺牲介质层以暴露所述沟槽侧壁的外延层;以及对所述重掺杂型多晶硅区域和沟槽侧壁的外延层同时进行氧化,以在沟槽的底部和侧壁上同步地分别形成厚氧层和沟槽侧壁栅介质层;其中,同步形成的所述厚氧层的厚度大于所述沟槽侧壁栅介质层的厚度,所述厚氧层用作所述沟槽场效应器件的沟槽底部栅介质层。该制备方法简单,并且制备形成的沟槽场效应器件的优值大大减小。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)