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1. (WO2013115900) REDUCING WEAK- ERASE TYPE READ DISTURB IN 3D NAND NON- VOLATILE MEMORY

Pub. No.:    WO/2013/115900    International Application No.:    PCT/US2012/066460
Publication Date: Fri Aug 09 01:59:59 CEST 2013 International Filing Date: Sat Nov 24 00:59:59 CET 2012
IPC: G11C 11/56
G11C 16/04
G11C 16/26
G11C 16/34
H01L 27/115
Applicants: SANDISK TECHNOLOGIES, INC.
DONG, Yingda
MUI, Man, L.
MIWA, Hitoshi
Inventors: DONG, Yingda
MUI, Man, L.
MIWA, Hitoshi
Title: REDUCING WEAK- ERASE TYPE READ DISTURB IN 3D NAND NON- VOLATILE MEMORY
Abstract:
A read process for a 3D stacked memory device provides an optimum level of channel boosting for unselected memory strings, to repress both normal and weak-erase types of read disturbs. The channel is boosted by controlling of voltages of bit lines (Vbl), drain-side select gates (Vsgd_unsel), source-side select gates (Vsgs_unsel), a selected level (word line layer) of the memory device (Vcg_sel), and unselected levels of the memory device (Vcg_unsel). A channel can be boosted by initially making the drain-side and source-side select gates non-conductive, to allow capacitive coupling from an increasing Vcg_unsel. The drain-side and/or source-side select gates are then made non- conductive by raising Vsgd_unsel and/or Vsgs_unsel, interrupting the boosting. Additionally boosting can occur by making the drain-side and/or source-side select gates conductive again while Vcg_unsel is still increasing. Or, the channel can be driven at Vbl. Two-step boosting drives the channel at Vbl, then provides boosting by capacitive coupling.