WIPO logo
Mobile | Deutsch | Español | Français | 日本語 | 한국어 | Português | Русский | 中文 | العربية |
PATENTSCOPE

Search International and National Patent Collections
World Intellectual Property Organization
Options
Query Language
Stem
Sort by:
List Length
Some content of this application is unavailable at the moment.
If this situation persist, please contact us atFeedback&Contact
1. (WO2013115790) SINGLE AND DOUBLE CHIP SPARE
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2013/115790 International Application No.: PCT/US2012/023313
Publication Date: 08.08.2013 International Filing Date: 31.01.2012
IPC:
G06F 13/16 (2006.01) ,G06F 11/07 (2006.01) ,G06F 11/10 (2006.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
13
Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14
Handling requests for interconnection or transfer
16
for access to memory bus
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
11
Error detection; Error correction; Monitoring
07
Responding to the occurrence of a fault, e.g. fault tolerance
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
11
Error detection; Error correction; Monitoring
07
Responding to the occurrence of a fault, e.g. fault tolerance
08
Error detection or correction by redundancy in data representation, e.g. by using checking codes
10
Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
Applicants: GOSTIN, Gary[US/US]; US (UsOnly)
HANDGEN, Erin[US/US]; US (UsOnly)
HEWLETT-PACKARD DEVELOPMENT COMPANY L.P.[US/US]; 11445 Compaq Center Drive West Houston, TX 77070, US (AllExceptUS)
Inventors: GOSTIN, Gary; US
HANDGEN, Erin; US
Agent: PAGAR, Preetam, B.; Hewlett Packard Company Intellectual Property Administration Mail Stop 35, P.O. Box 272400 Fort Collins, CO 80527-2400, US
Priority Data:
Title (EN) SINGLE AND DOUBLE CHIP SPARE
(FR) RÉSERVE À SIMPLE ET DOUBLE PUCE
Abstract:
(EN) Techniques are provided for overcoming failures in a memory. One portion of the memory may operate in a single chip spare mode. Upon detection of an error in a single chip in the portion of the memory, a region of the portion of the memory may be converted to operate in a double chip spare mode. The memory may be 'accessed in both single and double chip spare modes.
(FR) L'invention concerne des techniques permettant de surmonter des pannes dans une mémoire. Une partie de la mémoire peut fonctionner dans un mode de réserve à simple puce. Lors de la détection d'une erreur dans une simple puce dans la partie de la mémoire, une région de la partie de la mémoire peut être convertie afin de fonctionner dans un mode de réserve à double puce. La mémoire peut être accédée dans les deux modes de réserve à simple et à double puce.
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)