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1. (WO2013113184) SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2013/113184    International Application No.:    PCT/CN2012/072981
Publication Date: 08.08.2013 International Filing Date: 23.03.2012
IPC:
H01L 21/336 (2006.01), H01L 29/06 (2006.01), H01L 29/78 (2006.01)
Applicants: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES [CN/CN]; No.3 Beitucheng West Road, Chaoyang District Beijing 100029 (CN) (For All Designated States Except US).
ZHU, Huilong [US/US]; (US) (For US Only).
LUO, Zhijiong [US/US]; (US) (For US Only).
YIN, Haizhou [CN/US]; (US) (For US Only)
Inventors: ZHU, Huilong; (US).
LUO, Zhijiong; (US).
YIN, Haizhou; (US)
Agent: HANHOW INTELLECTUAL PROPERTY PARTNERS; ZHU, Haibo W1-1111, F/11 Oriental plaza, No.1 East Chang An Avenue, Dongcheng District Beijing 100738 (CN)
Priority Data:
201210022557.6 01.02.2012 CN
Title (EN) SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
(FR) STRUCTURE DE SEMICONDUCTEUR ET PROCÉDÉ POUR SA FABRICATION
(ZH) 一种半导体结构及其制造方法
Abstract: front page image
(EN)Provided are a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a substrate (130), a gate stack, a base area (100), and a source/drain area (150). The gate stack is above the base area (100). The source/drain area (150) is in the base area (100). The base area (100) is above the substrate (130). A support isolation structure (123) is provided between the base area (100) and the substrate (130). A part of the support isolation structure (123) is connected to the substrate (130). A cavity (112) is provided between the base area (100) and the substrate (130). The cavity (112) is formed by the base area (100), the substrate (130), and the support isolation structure (123). A stress material layer (113) is provided on two sides of the gate stack, the base area (100) and the support isolation structure (123).
(FR)L'invention concerne une structure de semiconducteur et un procédé pour sa fabrication. La structure de semiconducteur comporte un substrat (130), un empilement de grille, une zone (100) de base et une zone (150) de source / de drain. L'empilement de grille se trouve au-dessus de la zone (100) de base. La zone (150) de source / de drain se trouve dans la zone (100) de base. La zone (100) de base se trouve au-dessus du substrat (130). Une structure porteuse (123) d'isolement est placée entre la zone (100) de base et le substrat (130). Une partie de la structure porteuse (123) d'isolement est reliée au substrat (130). Une cavité (112) est ménagée entre la zone (100) de base et le substrat (130). La cavité (112) est formée par la zone (100) de base, le substrat (130), et la structure porteuse (123) d'isolement. Une couche (113) de matériau de contrainte est placée sur deux côtés de l'empilement de grille, de la zone (100) de base et de la structure porteuse (123) d'isolement.
(ZH)提供了一种半导体结构及其制造方法。半导体结构包括衬底(130)、栅堆叠、基底区(100)以及源/漏区(150);栅堆叠位于基底区(100)之上,源/漏区(150)位于基底区(100)内,基底区(100)位于衬底(130)之上;在基底区(100)和衬底(130)之间存在支撑隔离结构(123),部分支撑隔离结构(123)与衬底(130)相连接;在基底区(100)和衬底(130)之间存在空腔(112),空腔(112)由基底区(100)、衬底(130)以及支撑隔离结构(123)构成;在栅堆叠、基底区(100)和支撑隔离结构(123)的两侧存在应力材料层(113)。
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)