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1. (WO2013112763) DUAL MODE CLOCK/DATA RECOVERY CIRCUIT
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2013/112763 International Application No.: PCT/US2013/023025
Publication Date: 01.08.2013 International Filing Date: 24.01.2013
IPC:
H03L 7/08 (2006.01) ,H03L 7/087 (2006.01) ,H03L 7/091 (2006.01) ,H03L 7/14 (2006.01) ,H04L 7/033 (2006.01)
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
L
AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
7
Automatic control of frequency or phase; Synchronisation
06
using a reference signal applied to a frequency- or phase-locked loop
08
Details of the phase-locked loop
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
L
AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
7
Automatic control of frequency or phase; Synchronisation
06
using a reference signal applied to a frequency- or phase-locked loop
08
Details of the phase-locked loop
085
concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
087
using at least two phase detectors or a frequency and phase detector in the loop
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
L
AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
7
Automatic control of frequency or phase; Synchronisation
06
using a reference signal applied to a frequency- or phase-locked loop
08
Details of the phase-locked loop
085
concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
091
the phase or frequency detector using a sampling device
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
L
AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
7
Automatic control of frequency or phase; Synchronisation
06
using a reference signal applied to a frequency- or phase-locked loop
08
Details of the phase-locked loop
14
for assuring constant frequency when supply or correction voltages fail
H ELECTRICITY
04
ELECTRIC COMMUNICATION TECHNIQUE
L
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
7
Arrangements for synchronising receiver with transmitter
02
Speed or phase control by the received code signals, the signals containing no special synchronisation information
033
using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
Applicants:
QUALCOMM INCORPORATED [US/US]; Attn: International Ip Administration 5775 Morehouse Drive San Diego, California 92121, US (AllExceptUS)
Inventors:
ZHUANG, Jingcheng; US
DANG, Nam, V.; US
KONG, Xiaohua; US
ZHU, Zhi; US
SOWLATI, Tirdad; US
AMELIFARD, Behnam; US
Agent:
PAULEY, Nicholas, J.; 5775 Morehouse Drive San Diego, California 92121, US
Priority Data:
13/420,80015.03.2012US
61/590,29524.01.2012US
Title (EN) DUAL MODE CLOCK/DATA RECOVERY CIRCUIT
(FR) CIRCUIT DE RÉCUPÉRATION D'HORLOGE/DE DONNÉES EN BIMODE
Abstract:
(EN) A clock/data recovery circuit includes an edge detector circuit operable to receive a serial data burst and to generate a reset signal in response to a first edge of the serial data burst. The clock/data recovery circuit may also include an oscillator coupled to the edge detector circuit. The oscillator locks onto a target data rate prior to receipt of the serial data burst and locks onto a phase of the serial data burst in response to the reset signal. The clock/data recovery circuit may also include a phase detector circuit that receives the serial data burst. The phase detector circuit is coupled to the oscillator. The phase detector circuit adjusts the oscillator to maintain the lock onto the phase of the serial data burst during the serial data burst.
(FR) La présente invention a trait à un circuit de récupération d'horloge/de données qui inclut un circuit de détection de bord qui a pour fonction de recevoir un paquet de données en série et de générer un signal de réinitialisation en réponse à un premier bord du paquet de données en série. Le circuit de récupération d'horloge/de données peut également inclure un oscillateur qui est couplé au circuit de détection de bord. L'oscillateur se bloque sur un débit cible avant la réception du paquet de données en série et se bloque sur une phase du paquet de données en série en réponse au signal de réinitialisation. Le circuit de récupération d'horloge/de données peut aussi inclure un circuit de détection de phase qui reçoit le paquet de données en série. Le circuit de détection de phase est couplé à l'oscillateur. Le circuit de détection de phase ajuste l'oscillateur de manière à maintenir le verrouillage sur la phase du paquet de données en série au cours du paquet de données en série.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)