The disclosed clock-data recovery architecture includes out-of-lock (including false lock) detection. A clock-data recovery (CDR) circuit (100) for out-of-lock (including false lock) detection includes a phase/frequency detector (PFD) (101) for clock recovery and a data retimer (111) for recovering/retiming data. A received data signal is input to phase/frequency detector (101), which generates a recovered clock, and to retimer (111) which recovers and retimes data based on the recovered clock. Out-of-lock detection is accomplished by sampling retimed/recovered data with positive and negative edges of the received data. In example embodiments, an out-of-lock condition is determined either by detecting the occurrence of, or counting, missed edges corresponding to the failure of received data sampling to detect corresponding positive/negative edges of the retimed/recovered data.