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Machine translation
1. (WO2013111995) MULTILAYER PRINTED CIRCUIT BOARD AND METHOD FOR MANUFACTURING SAME
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2013/111995 International Application No.: PCT/KR2013/000620
Publication Date: 01.08.2013 International Filing Date: 25.01.2013
IPC:
H05K 3/46 (2006.01) ,H05K 3/40 (2006.01)
Applicants: AMOGREENTECH CO., LTD.[KR/KR]; 185-1, Sucham-ri, Tongjin-eup Gimpo-si, Gyeonggi-do 415-863, KR
Inventors: LEE, Young-Il; KR
YU, Jung-Sang; KR
Agent: HANYANG PATENT FIRM; (Dogok-dong, Hanyang building) 12 Nonhyenro 38-gil, Gangnam-gu Seoul 135-854, KR
Priority Data:
10-2012-000820527.01.2012KR
10-2012-000820627.01.2012KR
Title (EN) MULTILAYER PRINTED CIRCUIT BOARD AND METHOD FOR MANUFACTURING SAME
(FR) CARTE DE CIRCUITS IMPRIMÉS MULTICOUCHE ET SON PROCÉDÉ DE PRODUCTION
(KO) 다층 인쇄 회로 기판 및 이의 제조 방법
Abstract: front page image
(EN) A method for manufacturing a multilayer printed circuit board according to the present invention comprises: a step of preparing a substrate; a step of forming one or more via holes in the substrate; a step of forming a first conductive pattern including a conductive pattern covering lower openings of the via holes on a lower surface of the substrate; a step of filling the via holes with a conductive nanoparticle ink or a conductive nanoparticle paste comprising conductive nanoparticles; and a step of forming a second conductive pattern including a conductive pattern covering upper openings of the via holes on an upper surface of the substrate. According to the method of the present invention, via holes are filled with a conductive nanoparticle ink or a conductive nanoparticle paste including conductive nanoparticles so as to form vias, thus simplifying processes for forming vias, reducing costs and reducing problems of failures caused by the expansion and contraction deformation of a substrate.
(FR) L'invention concerne un procédé pour produire une carte de circuits imprimés comprenant : une étape qui consiste à préparer un substrat ; une étape qui consiste à former un ou plusieurs trous d'interconnexion dans le substrat; une étape qui consiste à former un premier réseau conducteur qui comprend un réseau conducteur recouvrant les ouvertures inférieures des trous d'interconnexion sur une surface inférieure du substrat ; une étape qui consiste à remplir les trous d'interconnexion au moyen d'une encre nanoparticulaire conductrice ou une pâte nanoparticulaire conductrice renfermant des nanoparticules conductrices ; et une étape qui consiste à former un deuxième réseau conducteur comprenant un réseau conducteur recouvrant les ouvertures supérieures des trous d'interconnexion dans la surface supérieure du substrat. Dans le procédé selon l'invention, les trous d'interconnexion sont remplis d'une encre nanoparticulaire conductrice ou d'une pâte nanoparticulaire conductrice renfermant des nanoparticules conductrices de manière à former des trous interconnexion, ce qui permet de simplifier les processus de formation de trous d'interconnexion, réduire les coûts et réduire les problèmes de défaillances causées par les déformations d'un substrat par expansion et contraction.
(KO) 본 발명에 따른 다층 인쇄 회로 기판의 제조 방법은, 기판을 준비하는 단계,상기 기판에 비아홀을 하나 이상 형성하는 단계, 상기 비아홀의 하부 개구부를 커버하는 도전 패턴을 포함하는 제1 도전 패턴을 상기 기판의 하면에 형성하는 단계, 상기 비아홀에 도전성 나노 입자를 포함하는 도전성 나노 입자 잉크 또는 도전성 나노 입자 페이스트를 충진하는 단계, 상기 비아홀의 상부 개구부를 커버하는 도전 패턴을 포함하는 제2 도전 패턴을 상기 기판의 상면에 형성하는 단계를 포함한다. 상기 방법에 의하면, 도전성 나노 입자를 포함하는 도전성 나노 입자 잉크 또는 도전성 나노 입자 페이스트로 비아홀을 충진하여 비아를 형성함으로써, 비아 형성 공정을 단순화하고 비용을 절감할 수 있으며, 기판 신축 변형에 따른 불량 발생 등의 문제를 줄일 수 있다.
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Korean (KO)
Filing Language: Korean (KO)