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1. (WO2013111533) THIN FILM TRANSISTOR SUBSTRATE MANUFACTURING METHOD, AND THIN FILM TRANSISTOR SUBSTRATE MANUFACTURED BY SAME
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2013/111533 International Application No.: PCT/JP2013/000163
Publication Date: 01.08.2013 International Filing Date: 16.01.2013
IPC:
H01L 29/786 (2006.01) ,G02F 1/1368 (2006.01) ,H01L 21/28 (2006.01) ,H01L 21/3205 (2006.01) ,H01L 21/336 (2006.01) ,H01L 21/768 (2006.01) ,H01L 23/532 (2006.01) ,H01L 29/417 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
G PHYSICS
02
OPTICS
F
DEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
1
Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
01
for the control of the intensity, phase, polarisation or colour
13
based on liquid crystals, e.g. single liquid crystal display cells
133
Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
136
Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
1362
Active matrix addressed cells
1368
in which the switching element is a three-electrode device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
28
Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/268158
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
3205
Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layers; After-treatment of these layers
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
768
Applying interconnections to be used for carrying current between separate components within a device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
522
including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
532
characterised by the materials
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40
Electrodes
41
characterised by their shape, relative sizes or dispositions
417
carrying the current to be rectified, amplified or switched
Applicants:
シャープ株式会社 SHARP KABUSHIKI KAISHA [JP/JP]; 大阪府大阪市阿倍野区長池町22番22号 22-22, Nagaike-cho, Abeno-ku, Osaka-shi, Osaka 5458522, JP
Inventors:
伊東 一篤 ITO, Kazuatsu; null
北角 英人 KITAKADO, Hidehito; null
Agent:
特許業務法人前田特許事務所 MAEDA & PARTNERS; 大阪府大阪市中央区本町2丁目5番7号 大阪丸紅ビル5階 Osaka-Marubeni Bldg.5F, 5-7, Hommachi 2-chome, Chuo-ku, Osaka-shi, Osaka 5410053, JP
Priority Data:
2012-01115723.01.2012JP
Title (EN) THIN FILM TRANSISTOR SUBSTRATE MANUFACTURING METHOD, AND THIN FILM TRANSISTOR SUBSTRATE MANUFACTURED BY SAME
(FR) PROCÉDÉ DE FABRICATION D'UN SUBSTRAT DE TRANSISTOR À COUCHE MINCE ET SUBSTRAT DE TRANSISTOR À COUCHE MINCE FABRIQUÉ PAR CE DERNIER
(JA) 薄膜トランジスタ基板の製造方法及びその方法により製造された薄膜トランジスタ基板
Abstract:
(EN) This thin film transistor substrate manufacturing method is provided with at least: a step of forming a source electrode (32) and a drain electrode (33), which are respectively configured of laminated films composed of first conductive films (32a, 33a) formed of titanium or molybdenum, second conductive films (32b, 33b) formed of copper, and third conductive films (32c, 33c) formed of titanium oxide; a step of forming a passivation film (18) on an oxide semiconductor layer (13), the source electrode (32), and the drain electrode (33), said passivation film being composed of an inorganic insulating film; and an annealing step of annealing the oxide semiconductor layer (13).
(FR) L'invention concerne un procédé de fabrication d'un substrat de transistor à couche mince doté d'au moins : une étape de formation d'une électrode source (32) et d'une électrode drain (33), qui sont respectivement constituées de films stratifiés se composant de premiers films conducteurs (32a, 33a) en titane ou molybdène, de deuxièmes films conducteurs (32b, 33b) en cuivre et de troisième films conducteurs (32c, 33c) en oxyde de titane ; une étape de formation d'un film de passivation (18) sur une couche semi-conductrice d'oxyde (13), l'électrode source (32) et l'électrode drain (33), ledit film de passivation se composant d'un film isolant inorganique ; et une étape de recuit consistant à recuire la couche semi-conductrice d'oxyde (13).
(JA)  チタンまたはモリブテンにより形成された第1導電膜(32a),(33a)と、銅により形成された第2導電膜(32b),(33b)と、酸化チタンにより形成された第3導電膜(32c),(33c)との積層膜により構成されたソース電極(32)及びドレイン電極(33)を形成する工程と、酸化物半導体層(13)、ソース電極(32)及びドレイン電極(33)上に、無機絶縁膜からなるパッシベーション膜(18)を形成する工程と、酸化物半導体層(13)に対してアニール処理を行うアニール処理工程とを少なくとも備える。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)