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1. (WO2013111533) THIN FILM TRANSISTOR SUBSTRATE MANUFACTURING METHOD, AND THIN FILM TRANSISTOR SUBSTRATE MANUFACTURED BY SAME
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2013/111533    International Application No.:    PCT/JP2013/000163
Publication Date: 01.08.2013 International Filing Date: 16.01.2013
IPC:
H01L 29/786 (2006.01), G02F 1/1368 (2006.01), H01L 21/28 (2006.01), H01L 21/3205 (2006.01), H01L 21/336 (2006.01), H01L 21/768 (2006.01), H01L 23/532 (2006.01), H01L 29/417 (2006.01)
Applicants: SHARP KABUSHIKI KAISHA [JP/JP]; 22-22, Nagaike-cho, Abeno-ku, Osaka-shi, Osaka 5458522 (JP)
Inventors: ITO, Kazuatsu; .
KITAKADO, Hidehito;
Agent: MAEDA & PARTNERS; Osaka-Marubeni Bldg.5F, 5-7, Hommachi 2-chome, Chuo-ku, Osaka-shi, Osaka 5410053 (JP)
Priority Data:
2012-011157 23.01.2012 JP
Title (EN) THIN FILM TRANSISTOR SUBSTRATE MANUFACTURING METHOD, AND THIN FILM TRANSISTOR SUBSTRATE MANUFACTURED BY SAME
(FR) PROCÉDÉ DE FABRICATION D'UN SUBSTRAT DE TRANSISTOR À COUCHE MINCE ET SUBSTRAT DE TRANSISTOR À COUCHE MINCE FABRIQUÉ PAR CE DERNIER
(JA) 薄膜トランジスタ基板の製造方法及びその方法により製造された薄膜トランジスタ基板
Abstract: front page image
(EN)This thin film transistor substrate manufacturing method is provided with at least: a step of forming a source electrode (32) and a drain electrode (33), which are respectively configured of laminated films composed of first conductive films (32a, 33a) formed of titanium or molybdenum, second conductive films (32b, 33b) formed of copper, and third conductive films (32c, 33c) formed of titanium oxide; a step of forming a passivation film (18) on an oxide semiconductor layer (13), the source electrode (32), and the drain electrode (33), said passivation film being composed of an inorganic insulating film; and an annealing step of annealing the oxide semiconductor layer (13).
(FR)L'invention concerne un procédé de fabrication d'un substrat de transistor à couche mince doté d'au moins : une étape de formation d'une électrode source (32) et d'une électrode drain (33), qui sont respectivement constituées de films stratifiés se composant de premiers films conducteurs (32a, 33a) en titane ou molybdène, de deuxièmes films conducteurs (32b, 33b) en cuivre et de troisième films conducteurs (32c, 33c) en oxyde de titane ; une étape de formation d'un film de passivation (18) sur une couche semi-conductrice d'oxyde (13), l'électrode source (32) et l'électrode drain (33), ledit film de passivation se composant d'un film isolant inorganique ; et une étape de recuit consistant à recuire la couche semi-conductrice d'oxyde (13).
(JA) チタンまたはモリブテンにより形成された第1導電膜(32a),(33a)と、銅により形成された第2導電膜(32b),(33b)と、酸化チタンにより形成された第3導電膜(32c),(33c)との積層膜により構成されたソース電極(32)及びドレイン電極(33)を形成する工程と、酸化物半導体層(13)、ソース電極(32)及びドレイン電極(33)上に、無機絶縁膜からなるパッシベーション膜(18)を形成する工程と、酸化物半導体層(13)に対してアニール処理を行うアニール処理工程とを少なくとも備える。
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)