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1. (WO2013111420) METHOD FOR PROCESSING BASE BODY TO BE PROCESSED
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2013/111420 International Application No.: PCT/JP2012/079140
Publication Date: 01.08.2013 International Filing Date: 09.11.2012
IPC:
H01L 21/3065 (2006.01) ,H01L 21/336 (2006.01) ,H01L 29/78 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
302
to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
306
Chemical or electrical treatment, e.g. electrolytic etching
3065
Plasma etching; Reactive-ion etching
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
Applicants:
東京エレクトロン株式会社 TOKYO ELECTRON LIMITED [JP/JP]; 東京都港区赤坂五丁目3番1号 3-1 Akasaka 5-chome, Minato-ku, Tokyo 1076325, JP
Inventors:
井上 雅喜 INOUE Masaki; US
小津 俊久 OZU Toshihisa; KR
谷川 雄洋 TANIKAWA Takehiro; JP
吉川 潤 YOSHIKAWA Jun; JP
Agent:
長谷川 芳樹 HASEGAWA Yoshiki; 東京都千代田区丸の内二丁目1番1号丸の内 MY PLAZA(明治安田生命ビル) 9階 創英国際特許法律事務所 SOEI PATENT AND LAW FIRM, Marunouchi MY PLAZA (Meiji Yasuda Life Bldg.) 9th fl., 1-1, Marunouchi 2-chome, Chiyoda-ku, Tokyo 1000005, JP
Priority Data:
2012-01336025.01.2012JP
Title (EN) METHOD FOR PROCESSING BASE BODY TO BE PROCESSED
(FR) PROCÉDÉ POUR TRAITER CORPS DE BASE DESTINÉ À ÊTRE TRAITÉ
(JA) 被処理基体の処理方法
Abstract:
(EN) One embodiment of the present invention provides a method for etching a second layer of a base body to be processed, said base body having exposed from the surface thereof a first layer containing Ni and Si, and the second layer containing Si and N. The method of the one embodiment includes: (a) a step wherein a base body to be processed is prepared in a processing chamber; and (b) a step wherein a first processing gas, which contains carbon and fluorine but not containing oxygen, is supplied to the inside of the processing chamber, and plasma is generated in the processing chamber.
(FR) La présente invention concerne un procédé pour graver une seconde couche d'un corps de base destiné à être traité, ledit corps de base comportant, exposée à partir de sa surface, une première couche qui contient Ni et Si, et la seconde couche qui contient Si et N. Le procédé de la présente invention comprend : (a) une étape dans laquelle un corps de base destiné à être traité est préparé dans une chambre de traitement ; et (b) une étape dans laquelle un premier gaz de traitement, qui contient du carbone et du fluor mais ne contient pas d'oxygène, est fourni à l'intérieur de la chambre de traitement, et du plasma est produit dans la chambre de traitement.
(JA)  一実施形態では、表面にNi及びSiを含む第1の層と、Si及びNを含む第2の層とが露出した被処理基体において、第2の層をエッチングする方法を提供する。一実施形態の方法は、(a)被処理基体を処理容器内において準備する工程と、(b)処理容器内に炭素及びフッ素を含み酸素を含まない第1の処理ガスを供給し、当該処理容器内においてプラズマを発生させる工程と、を含む。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)