Search International and National Patent Collections

1. (WO2013110664) OVERLAY MODEL FOR ALIGNING AND EXPOSING SEMICONDUCTOR WAFERS

Pub. No.:    WO/2013/110664    International Application No.:    PCT/EP2013/051249
Publication Date: Fri Aug 02 01:59:59 CEST 2013 International Filing Date: Thu Jan 24 00:59:59 CET 2013
IPC: H01L 21/68
G03F 7/20
G03F 9/00
Applicants: QONIAC GMBH
Inventors: HABETS, Boris
Title: OVERLAY MODEL FOR ALIGNING AND EXPOSING SEMICONDUCTOR WAFERS
Abstract:
A method of calculating an overlay correction model in an apparatus for the fabrication of a wafer comprising a structural pattern on a substrate and having first overlay marks generated in a first layer and second overlay marks in a second layer. Overlay deviations of a subset of overlay marks are measured providing a subset of overlay model parameters. For a plurality of overlay mark positions the overlay residuals are estimated using the subset of overlay model parameters. A set of process correction parameters derived from the overlay residuals is provided for the plurality of overlay mark positions. The subset of overlay marks is selected in dependence of the distance to the position of the exposure field, and the selected overlay marks are weighted based on the distance between the overlay mark position and the exposure field.