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1. WO2013100710 - STACKED SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

Publication Number WO/2013/100710
Publication Date 04.07.2013
International Application No. PCT/KR2012/011769
International Filing Date 28.12.2012
IPC
H01L 23/28 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
28Encapsulation, e.g. encapsulating layers, coatings
H01L 23/12 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
12Mountings, e.g. non-detachable insulating substrates
H01L 23/48 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
CPC
H01L 21/565
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, ; e.g. sealing of a cap to a base of a container
56Encapsulations, e.g. encapsulation layers, coatings
565Moulds
H01L 2224/02372
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
023Redistribution layers [RDL] for bonding areas
0237Disposition of the redistribution layers
02372connecting to a via connection in the semiconductor or solid-state body
H01L 2224/02375
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
023Redistribution layers [RDL] for bonding areas
0237Disposition of the redistribution layers
02375Top view
H01L 2224/02379
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
023Redistribution layers [RDL] for bonding areas
0237Disposition of the redistribution layers
02379Fan-out arrangement
H01L 2224/0345
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
03Manufacturing methods
034by blanket deposition of the material of the bonding area
03444in gaseous form
0345Physical vapour deposition [PVD], e.g. evaporation, or sputtering
H01L 2224/0346
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
03Manufacturing methods
034by blanket deposition of the material of the bonding area
0346Plating
Applicants
  • 주식회사 네패스 NEPES CO., LTD. [KR]/[KR]
Inventors
  • 권용태 KWON, Yong Tae
  • 이준규 LEE, Jun Kyu
Agents
  • 특허법인 세림 SELIM INTELLECTUAL PROPERTY LAW FIRM
Priority Data
10-2011-014551929.12.2011KR
Publication Language Korean (ko)
Filing Language Korean (KO)
Designated States
Title
(EN) STACKED SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF
(FR) BOÎTIER À SEMI-CONDUCTEURS EMPILÉS ET SON PROCÉDÉ DE FABRICATION
(KO) 적층형 반도체 패키지 및 그 제조 방법
Abstract
(EN) The present invention provides a stacked semiconductor package in which semiconductor chips having different sizes are stacked. The stacked semiconductor package according to one embodiment of the present invention comprises: a first semiconductor chip structure further comprising a first semiconductor chip, a first mold layer for surrounding the first semiconductor chip, and a first through via which penetrates the first mold layer and is electrically connected to the first semiconductor chip; and a second semiconductor chip structure which is stacked vertically with respect to the first semiconductor chip structure, and further comprises a second semiconductor chip and a second through via connected electrically to the first through via, wherein the size of the first semiconductor chip structure and the second semiconductor chip structure are the same.
(FR) La présente invention concerne un boîtier à semi-conducteurs empilés dans lequel des puces semi-conductrices présentant différentes tailles sont empilées. Le boîtier à semi-conducteurs empilés selon un mode de réalisation de la présente invention comprend : une première structure de puce semi-conductrice comprenant par ailleurs une première puce semi-conductrice, une première couche de moule destinée à entourer la première puce semi-conductrice et un premier trou traversant d'interconnexion pénétrant dans la première couche de moule et connecté électriquement à la première puce semi-conductrice; et une seconde structure de puce semi-conductrice empilée verticalement par rapport à la première structure de puce semi-conductrice et comprenant en outre une seconde puce semi-conductrice et un second trou d'interconnexion traversant connecté électriquement au premier trou d'interconnexion traversant, la taille de la première structure de puce semi-conductrice et de la seconde structure de puce semi-conductrice étant identiques.
(KO) 본 발명은, 서로 다른 크기를 가지는 반도체 칩이 적층된 적층형 반도체 패키지를 제공한다. 본 발명의 일실시예에 따른 적층형 반도체 패키지는, 제1 반도체 칩; 상기 제1 반도체 칩을 둘러싸는 제1 몰드층; 및 상기 제1 몰드층을 관통하고 상기 제1 반도체 칩과 전기적으로 연결된 제1 관통 전극;을 포함하는 제1 반도체 칩 구조체; 및 상기 제1 반도체 칩 구조체에 대하여 수직으로 적층되고, 제2 반도체 칩; 및 상기 제1 관통 전극과 전기적으로 연결된 제2 관통 전극;을 포함하는 상기 제2 반도체 칩 구조체; 를 포함하고, 상기 제1 반도체 칩 구조체와 상기 제2 반도체 칩 구조체는 서로 동일한 크기를 가진다.
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