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1. WO2013098643 - ADVANCED PROCESSOR ARCHITECTURE

Publication Number WO/2013/098643
Publication Date 04.07.2013
International Application No. PCT/IB2012/002997
International Filing Date 17.12.2012
IPC
G06F 9/38 2006.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
38Concurrent instruction execution, e.g. pipeline, look ahead
CPC
G06F 9/30189
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
30181Instruction operation extension or modification
30189according to execution mode, e.g. mode flag
G06F 9/355
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
34Addressing or accessing the instruction operand or the result ; ; Formation of operand address; Addressing modes
355Indexed addressing ; , i.e. using more than one address operand
G06F 9/3885
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
38Concurrent instruction execution, e.g. pipeline, look ahead
3885using a plurality of independent parallel functional units
G06F 9/3897
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
38Concurrent instruction execution, e.g. pipeline, look ahead
3885using a plurality of independent parallel functional units
3893controlled in tandem, e.g. multiplier-accumulator
3895for complex operations, e.g. multidimensional or interleaved address generators, macros
3897with adaptable data path
Applicants
  • HYPERION CORE INC. [US]/[US]
Inventors
  • VORBACH, Martin
Priority Data
11009911.616.12.2011EP
12001692.812.03.2012EP
12004331.006.06.2012EP
12004345.008.06.2012EP
Publication Language English (en)
Filing Language English (EN)
Designated States
Title
(EN) ADVANCED PROCESSOR ARCHITECTURE
(FR) ARCHITECTURE DE PROCESSEUR AVANCÉE
Abstract
(EN) The present invention relates to a processor core having an execution unit comprising an arrangement of Arithmetic-Logic- Units, wherein the operation mode of the execution unit is switchable between an asynchronous operation of the Arithmetic-Logic-Units and interconnection between the Arithmetic-Logic-Units such that a signal.from the register file crosses the execution unit and is receipt by the register file in one clock cycle; and wherein a pipelined operation mode of at least one of the Arithmetic-Logic-Units and the interconnection between the Arithmetic-Logic-Units such that a signal requires from the register file through the execution unit back to the register file more than one clock cycles.
(FR) La présente invention se rapporte à un cœur de processeur ayant une unité d'exécution qui comprend plusieurs unités arithmétiques logiques. Le mode de fonctionnement de ladite unité d'exécution peut alterner entre : un fonctionnement asynchrone des unités arithmétiques logiques et d'une interconnexion desdites unités arithmétiques logiques, où un signal en provenance de la pile de registres traverse l'unité d'exécution pour être reçu par la pile de registres en un cycle d'horloge; et un mode de fonctionnement en pipeline d'une ou plusieurs des unités arithmétiques logiques et de l'interconnexion desdites unités arithmétiques logiques, où un signal met moins d'un cycle d'horloge pour partir de la pile de registres et y revenir en passant par l'unité d'exécution.
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