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1. WO2013097582 - FLIP CHIP ON CHIP PACKAGE AND MANUFACTURING METHOD

Publication Number WO/2013/097582
Publication Date 04.07.2013
International Application No. PCT/CN2012/085818
International Filing Date 04.12.2012
IPC
H01L 21/60 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
60Attaching leads or other conductive members, to be used for carrying current to or from the device in operation
H01L 23/495 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
488consisting of soldered or bonded constructions
495Lead-frames
CPC
H01L 21/4825
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
4814Conductive parts
4821Flat leads, e.g. lead frames with or without insulating supports
4825Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
H01L 21/4828
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
4814Conductive parts
4821Flat leads, e.g. lead frames with or without insulating supports
4828Etching
H01L 21/561
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, ; e.g. sealing of a cap to a base of a container
56Encapsulations, e.g. encapsulation layers, coatings
561Batch processing
H01L 21/563
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, ; e.g. sealing of a cap to a base of a container
56Encapsulations, e.g. encapsulation layers, coatings
563Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
H01L 2224/16145
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
10Bump connectors; Manufacturing methods related thereto
15Structure, shape, material or disposition of the bump connectors after the connecting process
16of an individual bump connector
161Disposition
16135the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
16145the bodies being stacked
H01L 2224/32145
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
31Structure, shape, material or disposition of the layer connectors after the connecting process
32of an individual layer connector
321Disposition
32135the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
32145the bodies being stacked
Applicants
  • 北京工业大学 BEIJING UNIVERSITY OF TECHNOLOGY [CN]/[CN] (AllExceptUS)
  • 秦飞 QIN, Fei [CN]/[CN] (US)
  • 夏国峰 XIA, Guofeng [CN]/[CN] (US)
  • 安彤 AN, Tong [CN]/[CN] (US)
  • 刘程艳 LIU, Chengyan [CN]/[CN] (US)
  • 武伟 WU, Wei [CN]/[CN] (US)
  • 朱文辉 ZHU, Wenhui [SG]/[CN] (US)
Inventors
  • 秦飞 QIN, Fei
  • 夏国峰 XIA, Guofeng
  • 安彤 AN, Tong
  • 刘程艳 LIU, Chengyan
  • 武伟 WU, Wei
  • 朱文辉 ZHU, Wenhui
Agents
  • 北京思海天达知识产权代理有限公司 BEIJING SIHAI TIANDA INTELLECTCTUAL PORPERTY AGENT LTD.
Priority Data
201110457533.930.12.2011CN
Publication Language Chinese (zh)
Filing Language Chinese (ZH)
Designated States
Title
(EN) FLIP CHIP ON CHIP PACKAGE AND MANUFACTURING METHOD
(FR) PUCE RETOURNÉE SUR BOÎTIER PAVÉ ET PROCÉDÉ DE FABRICATION
(ZH) 一种芯片上倒装芯片封装及制造方法
Abstract
(EN) Disclosed is a flip chip on chip package and manufacturing method. The package includes a lead frame, a first and second metal material layer, a parent IC chip, a child IC chip having bumps, an insulation filler material, an adhesive material, a lower package and a plastic package material. The lead frame includes a chip carrier and a lead. The metal material layer is provided on the upper surface and the lower surface of the lead frame. The insulation filler material is provided under a step structure of the lead frame. The parent IC chip is provided at the first metal material layer location on the upper surface of the lead frame, and the child IC chip having bumps is provided on an insulated surface of the parent IC chip by way of inverted welding. The lower package is provided between the parent IC chip and the child IC chip having bumps. The plastic package material wraps the parent IC chip, the child IC chip having bumps, the adhesive material, the lower package, the first metal wire and the lead frame. The present invention provides a 3D package structure based on QFN package with high reliability, low costs and high I/O density.
(FR) La présente invention a trait à une puce retournée sur un boîtier pavé et à un procédé de fabrication. Le boîtier inclut une grille de connexion, une première et une seconde couche de métal, une puce de CI parent, une puce de CI enfant qui est dotée de bosses, un matériau de remplissage isolant, un matériau adhésif, un boîtier inférieur et un matériau de boîtier de plastique. La grille de connexion inclut un boîtier pavé et une broche de raccordement. La couche de métal est prévue sur la surface supérieure et sur la surface inférieure de la grille de connexion. Le matériau de remplissage isolant est prévu sous une structure étagée de la grille de connexion. La puce de CI parent est prévue sur l'emplacement de la première couche de métal sur la surface supérieure de la grille de connexion et la puce de CI enfant qui est dotée de bosses est prévue sur une surface isolée de la puce de CI parent au moyen d'un soudage autogène inversé. Le boîtier inférieur est prévu entre la puce de CI parent et la puce de CI enfant qui est dotée de bosses. Le matériau de boîtier de plastique enveloppe la puce de CI parent, la puce de CI enfant qui est dotée de bosses, le matériau adhésif, le boîtier inférieur, le premier fil de métal et la grille de connexion. La présente invention fournit une structure de boîtier 3D en se basant sur un boîtier QFN avec une grande fiabilité, de faibles coûts et une densité E/S élevée.
(ZH) 本发明公开了一种芯片上倒装芯片封装及制造方法。本封装包括引线框架、第一、第二金属材料层、母IC芯片、具有凸点的子IC芯片、绝缘填充材料、粘贴材料、下填料和塑封材料。引线框架包括芯片载体和引脚。金属材料层配置于引线框架上表面和下表面。绝缘填充材料配置于引线框架的台阶式结构下。母IC芯片通过粘贴材料配置于引线框架上表面的第一金属材料层位置,具有凸点的子IC芯片倒转焊接配置于母IC芯片的有缘面上。下填料配置于母IC芯片与具有凸点的子IC芯片之间。塑封材料包覆母IC芯片、具有凸点的子IC芯片、粘贴材料、下填料、第一金属导线和引线框架。本发明提供了基于QFN封装的高可靠性、低成本、高I/O密度的三维封装结构。
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