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1. (WO2013095651) NON-PLANAR GATE ALL-AROUND DEVICE AND METHOD OF FABRICATION THEREOF
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2013/095651 International Application No.: PCT/US2011/067234
Publication Date: 27.06.2013 International Filing Date: 23.12.2011
IPC:
H01L 29/78 (2006.01) ,H01L 21/336 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
Applicants:
RACHMADY, Willy [US/US]; US (UsOnly)
PILLARISETTY, Ravi [US/US]; US (UsOnly)
LE, Van H. [US/US]; US (UsOnly)
KAVALIEROS, Jack T. [US/US]; US (UsOnly)
CHAU, Robert S. [US/US]; US (UsOnly)
KACHIAN, Jessica Sevanne [US/US]; US (UsOnly)
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard MS: RNB-4-150 Santa Clara, California 95052, US (AllExceptUS)
Inventors:
RACHMADY, Willy; US
PILLARISETTY, Ravi; US
LE, Van H.; US
KAVALIEROS, Jack T.; US
CHAU, Robert S.; US
KACHIAN, Jessica Sevanne; US
Agent:
BRASK, Justin K.; Blakely, Sokoloff, Taylor & Zafman LLP 1279 Oakmead Parkway Sunnyvale, California 94085-4040, US
Common
Representative:
RACHMADY, Willy [US/US]; 10945 SW Nutcracker Ct. Beaverton, Oregon 97007, US
Priority Data:
Title (EN) NON-PLANAR GATE ALL-AROUND DEVICE AND METHOD OF FABRICATION THEREOF
(FR) GRILLE NON PLANAIRE TOUT AUTOUR D'UN DISPOSITIF ET SON PROCÉDÉ DE FABRICATION
Abstract:
(EN) A non-planar gate all-around device and method of fabrication thereby are described. In one embodiment, the device includes a substrate having a top surface with a first lattice constant. Embedded epi source and drain regions are formed on the top surface of the substrate. The embedded epi source and drain regions have a second lattice constant that is different from the first lattice constant. Channel nanowires having a third lattice are formed between and are coupled to the embedded epi source and drain regions. In an embodiment, the second lattice constant and the third lattice constant are different from the first lattice constant. The channel nanowires include a bottom-most channel nanowire and a bottom gate isolation is formed on the top surface of the substrate under the bottom-most channel nanowire. A gate dielectric layer is formed on and all-around each channel nanowire. A gate electrode is formed on the gate dielectric layer and surrounding each channel nanowire.
(FR) L'invention concerne une grille non planaire tout autour d'un dispositif et son procédé de fabrication. Dans un mode de réalisation, le dispositif comprend un substrat ayant une surface supérieure avec une première constante de réseau cristallin. Des zones de source et de drain epi incorporées sont formées sur la surface supérieure du substrat. Les zones de source et de drain epi incorporées ont une deuxième constante de réseau cristallin qui est différente de la première constante de réseau cristallin. Des nanofils de canal ayant un troisième réseau cristallin sont formés entre et son couplés aux zones de source et de drain epi incorporées. Dans un mode de réalisation, la deuxième constante de réseau cristallin et la troisième constante de réseau cristallin sont différentes de la première constante de réseau cristallin. Les nanofils de canal comprennent un nanofil de canal inférieur et une isolation de grille inférieure est formée sur la surface supérieure du substrat sous le nanofil de canal inférieur. Une couche diélectrique de grille est formée sur et tout autour de chaque nanofil de canal. Une électrode de grille est formée sur la couche diélectrique de grille et entoure chaque nanofil de canal.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)