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Machine translation
1. (WO2013058447) MULTI-TRANSISTOR
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2013/058447    International Application No.:    PCT/KR2012/002081
Publication Date: 25.04.2013 International Filing Date: 22.03.2012
IPC:
H01L 27/085 (2006.01)
Applicants: SOONGSIL UNIVERSITY RESEARCH CONSORTIUM TECHNO-PARK [KR/KR]; 511, Sangdo-dong, Dongjak-gu, Seoul 156-030 (KR) (For All Designated States Except US).
PARK, Jong-Hoon [KR/KR]; (KR) (For US Only).
PARK, Chang-Kun [KR/KR]; (KR) (For US Only)
Inventors: PARK, Jong-Hoon; (KR).
PARK, Chang-Kun; (KR)
Agent: TAEBAEK INTELLECTUAL PROPERTY LAW FIRM; #906, Kolon technovalley 60-4 Gasan-dong, Geumcheon-gu Seoul 153-770 (KR)
Priority Data:
10-2011-0105892 17.10.2011 KR
Title (EN) MULTI-TRANSISTOR
(FR) MULTI-TRANSISTOR
(KO) 멀티 트랜지스터
Abstract: front page image
(EN)The present invention relates to a multi-transistor and a method of manufacturing same. The multi-transistor according to an embodiment of the present invention includes: a first transistor including a gate, a first source formed on one side of the gate, and a first drain formed on the other side of the gate; and a second transistor including a second drain formed oppositely to the first source and on the one side of the gate on a substrate, and a second source formed oppositely to the first drain and on the other side of the gate, so as to minimize parasite inductance components occurring between opposite transistors.
(FR)La présente invention concerne un multi-transistor et un procédé pour sa fabrication. Le multi-transistor selon un mode de réalisation de la présente invention comprend : un premier transistor comprenant une grille, une première source formée d'un côté de la grille et un premier drain formé de l'autre côté de la grille ; et un deuxième transistor comprenant un deuxième drain formé à l'opposé de la première source et dudit côté de la grille sur un substrat et une deuxième source formée à l'opposé du premier drain et de l'autre côté de la grille, de façon à minimiser les composantes d'inductance parasite survenant entre des transistors opposés.
(KO)본 발명은 멀티 트랜지스터 및 그 제조방법에 관한 것으로, 본 발명의 일 실시예에 따른 멀티 트랜지스터는, 게이트와, 상기 게이트의 일 측에 형성되는 제1 소스와, 상기 게이트의 타 측에 형성되는 제1 드레인을 포함하는 제1 트랜지스터와, 상기 기판에 상기 제1 소스와 대향하여 상기 게이트의 일 측에 형성되는 제2 드레인과, 상기 제1 드레인과 대향하여 상기 게이트의 타 측에 형성되는 제2 소스를 포함하는 제2 트랜지스터를 포함함으로써, 대향하는 트랜지스터에서 발생하는 기생 인덕턴스 성분을 최소화할 수 있다.
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: Korean (KO)
Filing Language: Korean (KO)