WIPO logo
Mobile | Deutsch | Español | Français | 日本語 | 한국어 | Português | Русский | 中文 | العربية |
PATENTSCOPE

Search International and National Patent Collections
World Intellectual Property Organization
Search
 
Browse
 
Translate
 
Options
 
News
 
Login
 
Help
 
Machine translation
1. (WO2013056249) THREE DIMENSIONAL ARCHITECTURE SEMICONDUCTOR DEVICES AND ASSOCIATED METHODS
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2013/056249    International Application No.:    PCT/US2012/060291
Publication Date: 18.04.2013 International Filing Date: 15.10.2012
IPC:
H01L 27/146 (2006.01), H01L 27/14 (2006.01)
Applicants: SIONYX, INC. [US/US]; 100 Cummings Ctr., Suite 243-F Beverly, Massachusetts 01915-6506 (US) (For All Designated States Except US).
HADDAD, Homayoon [US/US]; (US) (US only).
FORBES, Leonard [US/US]; (US) (US only)
Inventors: HADDAD, Homayoon; (US).
FORBES, Leonard; (US)
Agent: ALDER, Todd, B.; P.O. Box 1219 Sandy, Utah 84091-1219 (US)
Priority Data:
61/546,896 13.10.2011 US
13/621,737 17.09.2012 US
Title (EN) THREE DIMENSIONAL ARCHITECTURE SEMICONDUCTOR DEVICES AND ASSOCIATED METHODS
(FR) DISPOSITIFS SEMI-CONDUCTEURS À ARCHITECTURE TRIDIMENSIONNELLE ET PROCÉDÉS ASSOCIÉS
Abstract: front page image
(EN)Semiconductor devices having three dimensional (3D) architectures and methods form making such devices are provided. In one aspect, for example, a method for making a semiconductor device can include forming a device layer on a front side of a semiconductor layer that is substantially defect free, bonding a carrier substrate to the device layer, processing the semiconductor layer on a back side opposite the device layer to form a processed surface, and bonding a smart substrate to the processed surface. In some aspects, the method can also include removing the carrier substrate from the semiconductor layer to expose the device layer.
(FR)La présente invention concerne des dispositifs semi-conducteurs à architecture tridimensionnelle (3D) et des procédés de fabrication de ces dispositifs. Par exemple, selon un aspect, un procédé de fabrication d'un dispositif semi-conducteur peut comprendre les étapes consistant à former une couche du dispositif sur une surface avant d'une couche semi-conductrice sensiblement sans défaut, coller un substrat de support à la couche du dispositif, traiter la couche semi-conductrice sur une surface arrière en regard de la couche du dispositif de façon à former une surface traitée et coller un substrat évolué à la surface traitée. Selon certains aspects, le procédé peut également comprendre une étape consistant à retirer le substrat de support de la couche semi-conductrice de façon à exposer la couche du dispositif.
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)