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1. (WO2013054958) NONVOLATILE MEMORY DEVICE HAVING A 3-DIMENSIONAL STRUCTURE, METHOD OF MANUFACTURING SAME, AND MEMORY CHIP
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2013/054958    International Application No.:    PCT/KR2011/007629
Publication Date: 18.04.2013 International Filing Date: 13.10.2011
IPC:
H01L 27/115 (2006.01), H01L 21/8247 (2006.01)
Applicants: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY [KR/KR]; 373-1 Guseong-dong, Yuseong-gu Daejeon 305-701 (KR) (For All Designated States Except US).
LEE, Wan Gyu [KR/KR]; (KR) (For US Only).
KIM, Jung Woo [KR/KR]; (KR) (For US Only)
Inventors: LEE, Wan Gyu; (KR).
KIM, Jung Woo; (KR)
Agent: KIM, Nam-Sik; Yulmin IP Law Firm 2nd Floor, Nice Building 28, Saimdang-ro, Seocho-Gu Seoul 137-876 (KR)
Priority Data:
Title (EN) NONVOLATILE MEMORY DEVICE HAVING A 3-DIMENSIONAL STRUCTURE, METHOD OF MANUFACTURING SAME, AND MEMORY CHIP
(FR) DISPOSITIF À MÉMOIRE NON VOLATILE AYANT UNE STRUCTURE EN 3 DIMENSIONS, UN PROCÉDÉ DE FABRICATION DE CELUI-CI ET PUCE MÉMOIRE
(KO) 3차원 구조의 비휘발성 메모리 소자, 그 제조 방법 및 메모리 칩
Abstract: front page image
(EN)Provided are a nonvolatile memory device having a 3-dimensional structure, a method of manufacturing same, and a memory chip. In the nonvolatile memory device, at least one NAND string is provided on a substrate. The at least one NAND string includes at least one semiconductor pillar extending upward toward the substrate and a plurality of memory cells connected in series along the at least one semiconductor pillar. The at least one semiconductor pillar includes at least one lateral expansion part within each of the NAND strings.
(FR)L'invention concerne un dispositif à mémoire non volatile qui présente une structure en 3 dimensions, un procédé de fabrication de celui-ci et une puce mémoire. Dans le dispositif à mémoire non volatile, au moins une chaîne NAND est prévue sur un substrat. La au moins une chaîne NAND comprend au moins un pilier à semi-conducteurs qui s'étend vers le haut vers le substrat et une pluralité de cellules mémoire connectées en série le long du au moins un pilier à semi-conducteurs. Le au moins un pilier à semi-conducteurs comprend au moins une partie d'expansion latérale à l'intérieur de chacune des chaînes NAND.
(KO)3차원 구조의 비휘발성 메모리 소자, 그 제조 방법 및 메모리 칩이 제공된다. 비휘발성 메모리 소자에 따르면, 적어도 하나의 낸드 스트링은 기판 상에 제된다. 상기 적어도 하나의 낸드 스트링은 상기 기판 상으로 상향 신장된 적어도 하나의 반도체 기둥 및 상기 적어도 하나의 반도체 기둥을 따라 직렬로 연결된 복수의 메모리셀들을 포함한다. 상기 적어도 하나의 반도체 기둥은 각 낸드 스트링 내에 적어도 하나의 측방향 확장부를 포함한다.
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: Korean (KO)
Filing Language: Korean (KO)