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1. WO2013052080 - STUB MINIMIZATION FOR MULTI-DIE WIREBOND ASSEMBLIES WITH ORTHOGONAL WINDOWS

Publication Number WO/2013/052080
Publication Date 11.04.2013
International Application No. PCT/US2012/000425
International Filing Date 03.10.2012
IPC
H01L 25/065 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04the devices not having separate containers
065the devices being of a type provided for in group H01L27/78
H01L 23/498 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
488consisting of soldered or bonded constructions
498Leads on insulating substrates
H01L 25/10 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
10the devices having separate containers
CPC
G11C 5/02
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
5Details of stores covered by G11C11/00
02Disposition of storage elements, e.g. in the form of a matrix array
G11C 5/04
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
5Details of stores covered by G11C11/00
02Disposition of storage elements, e.g. in the form of a matrix array
04Supports for storage elements ; , e.g. memory modules; Mounting or fixing of storage elements on such supports
G11C 5/06
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
5Details of stores covered by G11C11/00
06Arrangements for interconnecting storage elements electrically, e.g. by wiring
G11C 5/063
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
5Details of stores covered by G11C11/00
06Arrangements for interconnecting storage elements electrically, e.g. by wiring
063Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
G11C 8/06
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
8Arrangements for selecting an address in a digital store
06Address interface arrangements, e.g. address buffers
G11C 8/10
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
8Arrangements for selecting an address in a digital store
10Decoders
Applicants
  • INVENSAS CORPORATION [US]/[US]
Inventors
  • CRISP, Richard, Dewitt
  • ZOHNI, Wael
  • HABA, Belgacem
  • LAMBRECHT, Frank
Agents
  • NEFF, Daryl, K.
Priority Data
13/337,56527.12.2011US
13/337,57527.12.2011US
13/354,74720.01.2012US
13/354,77220.01.2012US
13/439,22804.04.2012US
13/439,27304.04.2012US
13/439,31704.04.2012US
13/440,19905.04.2012US
13/440,21205.04.2012US
13/440,28005.04.2012US
13/440,51505.04.2012US
13/595,48627.08.2012US
61/542,48803.10.2011US
61/542,49503.10.2011US
61/542,55303.10.2011US
61/600,48317.02.2012US
61/600,52717.02.2012US
Publication Language English (en)
Filing Language English (EN)
Designated States
Title
(EN) STUB MINIMIZATION FOR MULTI-DIE WIREBOND ASSEMBLIES WITH ORTHOGONAL WINDOWS
(FR) RÉDUCTION AU MINIMUM DES STUBS POUR MONTAGES À CONNEXIONS DES FILS À DÉS MULTIPLES AVEC FENÊTRES ORTHOGONALES
Abstract
(EN) A microelectronic structure (100) has active elements (202) defining a memory storage array (204), and address inputs (206) for receipt of address information specifying locations within the storage array. The structure has a first surface (201) and can have terminals (104, 106) exposed at the first surface. The terminals may include first terminals (104) and the structure may be configured to transfer address information received at the first terminals to the address inputs. Each first terminal can have a signal assignment which includes one or more of the address inputs. The first terminals are disposed on first and second opposite sides of a theoretical plane (132) normal to the first surface, wherein the signal assignments of the first terminals disposed on the first side are a mirror image of the signal assignments of the first terminals disposed on the second side of the theoretical plane.
(FR) Une structure micro-électronique (100) possède des éléments actifs (202) définissant une matrice de mémoire (204), et des entrées d'adresse (206) pour la réception des informations d'adresse spécifiant les emplacements dans la matrice de mémoire. La structure possède une première surface (201) et peut posséder des bornes (104, 106) exposées au niveau de la première surface. Les bornes peuvent comporter des premières bornes (104) et la structure peut être configurée pour transférer aux entrées d'adresse des informations d'adresse reçues au niveau des premières bornes. Chaque première borne peut posséder une attribution de signal qui comprend une ou plusieurs des entrées d'adresse. Les premières bornes sont disposées sur les premier et deuxième côtés opposés d'un plan théorique (132) normal à la première surface, les attributions de signal des premières bornes disposées sur le premier côté sont une image miroir des attribution de signal des premières bornes disposées sur le deuxième côté du plan théorique.
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