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Machine translation
1. (WO2013049186) PROGRAMMABLE LOGIC SENSING IN MAGNETIC RANDOM ACCESS MEMORY
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2013/049186    International Application No.:    PCT/US2012/057310
Publication Date: 04.04.2013 International Filing Date: 26.09.2012
Chapter 2 Demand Filed:    26.07.2013    
IPC:
G11C 11/16 (2006.01), H03K 19/20 (2006.01), H03K 19/173 (2006.01), G11C 13/00 (2006.01)
Applicants: QUALCOMM INCORPORATED [US/US]; Attn: International IP Administration 5775 Morehouse Drive San Diego, California 92121 (US) (For All Designated States Except US).
KIM, Jung Pill [US/US]; (US) (US only).
KIM, Tae Hyun [KR/US]; (US) (US only).
WU, Wenqing [US/US]; (US) (US only).
ZHU, Xiaochun [CN/US]; (US) (US only).
KANG, Seung H. [US/US]; (US) (US only)
Inventors: KIM, Jung Pill; (US).
KIM, Tae Hyun; (US).
WU, Wenqing; (US).
ZHU, Xiaochun; (US).
KANG, Seung H.; (US)
Agent: TALPALATSKY, Sam; 5775 Morehouse Drive San Diego, California 92121 (US)
Priority Data:
13/244,962 26.09.2011 US
Title (EN) PROGRAMMABLE LOGIC SENSING IN MAGNETIC RANDOM ACCESS MEMORY
(FR) DÉTECTION D'UNE LOGIQUE PROGRAMMABLE DANS UNE MÉMOIRE VIVE MAGNÉTIQUE
Abstract: front page image
(EN)A Magnetic Random Access Memory (MRAM) logic circuit (302) includes read sensing circuitry (208, 300) having a first level corresponding to a first category of logic circuitry and a second logic level corresponding to a second category of logic circuitry. The logic circuitry (302) may be switchable between circuitry having the first logic level and circuitry having the second logic level according to the category of the logic circuit being implemented.
(FR)Un circuit logique (302) de mémoire vive magnétique (MRAM) comprend des circuits de détection de lecture (208, 300) ayant un premier niveau logique correspondant à une première catégorie de circuits logiques et un second niveau logique correspondant à une seconde catégorie de circuits logiques. Les circuits logiques (302) peuvent être commutés entre des circuits ayant le premier niveau logique et des circuits ayant le second niveau logique en fonction de la catégorie du circuit logique implémenté.
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)