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1. (WO2013048155) METHOD FOR FORMING FINE PATTERNS OF SEMICONDUCTOR DEVICE USING DIRECTED SELF ASSEMBLY PROCESS
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2013/048155    International Application No.:    PCT/KR2012/007837
Publication Date: 04.04.2013 International Filing Date: 27.09.2012
IPC:
H01L 21/027 (2006.01)
Applicants: DONGJIN SEMICHEM CO., LTD. [KR/KR]; 644, Baekbeom-ro, Seo-ku, Incheon 404-817 (KR)
Inventors: LEE, Jung-Youl; (KR).
JANG, Eu-Jean; (KR).
LEE, Jae-Woo; (KR).
KIM, Jae-Hyun; (KR)
Agent: LEE, Sang-Hun; Han Nuri Patent & Law Office 2nd Fl. 15-4, Teheran-ro 25-gil Gangnam-gu Seoul 135-910 (KR)
Priority Data:
10-2011-0098838 29.09.2011 KR
Title (EN) METHOD FOR FORMING FINE PATTERNS OF SEMICONDUCTOR DEVICE USING DIRECTED SELF ASSEMBLY PROCESS
(FR) PROCÉDÉ DE FORMATION DE MOTIFS FINS DE DISPOSITIF À SEMI-CONDUCTEURS UTILISANT UN PROCESSUS D'AUTO-ASSEMBLAGE DIRIGÉ
(KO) 유도된 자가정렬 공정을 이용한 반도체 소자의 미세패턴 형성 방법
Abstract: front page image
(EN)A method for forming fine patterns of a semiconductor device, which can form patterns having a size of pattern line width of 20nm or less without a bulk exposure and hardening process for a guide pattern, includes: an (a) step of forming a photoresist layer on a substrate having an organic anti-reflection layer; a (b) step of forming a guide pattern by exposing the photoresist layer and developing the exposed photoresist layer using a negative tone developer; (c) step of forming a self assembly conductive layer on the substrate having the guide pattern; a (d) step of forming the self assembly conductive layer by removing the guide pattern using the developer; an (e) step of coating a block copolymer as a directed self assembly (DSA) material on the substrate coated with the self assembly conductive layer from which the guide pattern is removed, and forming self-assembled patterns by heating the block copolymer at the glass transition temperature or higher; and a (f) step of forming the fine patterns by selectively etching a part having a low resistance against the etching (or having a high etching speed) among the self-assembled patterns using O2 plasma.
(FR)Un procédé de formation de motifs fins d'un dispositif à semi-conducteurs, qui peut former des motifs ayant une taille de largeur de trait de motif de 20 nm ou moins sans processus de durcissement et d'exposition de masse pour un motif de guidage, comprend : une (a) étape consistant à former une couche photorésistante sur un substrat possédant une couche antireflet organique ; une (b) étape consistant à former un motif de guidage par exposition de la couche photorésistante et par développement de la couche photorésistante exposée à l'aide d'un développeur de ton négatif ; une (c) étape consistant à former une couche conductrice d'auto-assemblage sur le substrat comportant le motif de guidage ; une (d) étape consistant à former la couche conductrice d'auto-assemblage par retrait du motif de guidage à l'aide du développeur ; une (e) étape consistant à étaler un copolymère séquencé comme matériau d'auto-assemblage dirigé (DSA) sur le substrat recouvert de la couche conductrice d'auto-assemblage de laquelle est retiré le motif de guidage, et à former des motifs auto-assemblés par chauffage du copolymère séquencé à la température de transition vitreuse ou plus ; et une (f) étape consistant à former les motifs fins par gravure sélective d'une partie ayant une faible résistance à la gravure (ou ayant une vitesse de gravure élevée) parmi les motifs auto-assemblés à l'aide d'un plasma O2.
(KO)가이드 패턴의 벌크 노광 및 경화 과정 없이, 패턴 선폭의 사이즈가 20nm 이하인 패턴을 형성할 수 있는, 반도체 소자의 미세패턴 형성 방법은 (a) 유기반사방지막이 형성된 기판 위에 포토레지스트막을 형성하는 단계; (b) 상기 포토레지스트막을 노광하고, 네가티브 톤 현상액으로 현상하여 가이드 패턴을 형성하는 단계; (c) 상기 가이드 패턴이 형성된 기판 위에 자가정렬 유도층을 형성하는 단계; (d) 현상액을 이용하여 상기 가이드 패턴을 제거하여, 자가정렬 유도층을 형성하는 단계; (e) 상기 가이드 패턴이 제거된 자가정렬 유도층이 코팅된 기판 위에 DSA(directed self assembly) 물질인 블록 공중합체를 코팅하고, 상기 블록 공중합체의 유리전이온도 이상의 온도로 가열하여 자가정렬된 패턴을 형성하는 단계; 및 (f) 자가정렬된 패턴 중, 식각에 대한 저항성이 작은(또는 식각속도가 빠른) 부분을 산소(O2) 플라즈마를 이용하여 선택적으로 식각하여 미세패턴을 형성하는 단계를 포함한다.
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: Korean (KO)
Filing Language: Korean (KO)