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1. WO2013046680 - CIRCUIT DEVICE

Publication Number WO/2013/046680
Publication Date 04.04.2013
International Application No. PCT/JP2012/006170
International Filing Date 27.09.2012
IPC
H01L 21/52 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
52Mounting semiconductor bodies in containers
B23K 1/00 2006.1
BPERFORMING OPERATIONS; TRANSPORTING
23MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
KSOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
1Soldering, e.g. brazing, or unsoldering
B23K 1/19 2006.1
BPERFORMING OPERATIONS; TRANSPORTING
23MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
KSOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
1Soldering, e.g. brazing, or unsoldering
19taking account of the properties of the materials to be soldered
B23K 1/20 2006.1
BPERFORMING OPERATIONS; TRANSPORTING
23MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
KSOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
1Soldering, e.g. brazing, or unsoldering
20Preliminary treatment of work or areas to be soldered, e.g. in respect of a galvanic coating
B23K 20/00 2006.1
BPERFORMING OPERATIONS; TRANSPORTING
23MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
KSOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
20Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating
H01L 23/36 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
34Arrangements for cooling, heating, ventilating or temperature compensation
36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heat sinks
CPC
H01L 2224/0345
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
03Manufacturing methods
034by blanket deposition of the material of the bonding area
03444in gaseous form
0345Physical vapour deposition [PVD], e.g. evaporation, or sputtering
H01L 2224/04026
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
04026Bonding areas specifically adapted for layer connectors
H01L 2224/04042
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
04042Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
H01L 2224/05084
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
05001Internal layers
05075Plural internal layers
0508being stacked
05084Four-layer arrangements
H01L 2224/05124
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
05001Internal layers
05099Material
051with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
05117the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
05124Aluminium [Al] as principal constituent
H01L 2224/05139
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
05001Internal layers
05099Material
051with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
05138the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
05139Silver [Ag] as principal constituent
Applicants
  • 三洋電機株式会社 SANYO ELECTRIC CO., LTD. [JP]/[JP]
Inventors
  • 齋藤 浩一 SAITOU, Kouichi
  • 中里 真弓 NAKASATO, Mayumi
  • 岡山 芳央 OKAYAMA, Yoshio
Agents
  • 森下 賢樹 MORISHITA, Sakaki
Priority Data
2011-21707430.09.2011JP
Publication Language Japanese (ja)
Filing Language Japanese (JA)
Designated States
Title
(EN) CIRCUIT DEVICE
(FR) DISPOSITIF DE CIRCUIT
(JA) 回路装置
Abstract
(EN) A circuit device (50) of one embodiment of the present invention comprises a ceramic substrate (52), a first electroconductive pattern (53) provided on one surface of the ceramic substrate (52), a second electroconductive pattern (54) having Cu as the main component provided on the other surface of the ceramic substrate (52), and a semiconductor element (55) provided on an island (56) constituting the second electroconductive pattern (54). An electrode having an outermost layer having Cu as the main component is provided to the semiconductor element (55), and the interface between the island (56) and the electrode is directly adhered by solid-phase bonding.
(FR) La présente invention concerne, selon un mode de réalisation, un dispositif de circuit (5) qui comprend un substrat en céramique (52), un premier motif électroconducteur (53) disposé sur une surface du substrat en céramique (52), un second motif électroconducteur (54) ayant Cu en tant que composant principal, disposé sur l'autre surface du substrat en céramique (52), et un élément semi-conducteur (55) disposé sur un îlot (56) constituant le second motif électroconducteur (54). Une électrode ayant la couche la plus à l'extérieur ayant Cu comme composant principal est disposée sur l'élément semi-conducteur (55), et l'interface entre l'îlot (56) et l'électrode est directement adhérée par liaison par diffusion.
(JA)  本発明のある態様の回路装置50は、セラミック基板52と、セラミック基板52の一方の面に設けられた第1の導電パターン53と、セラミック基板52の他方の面に設けられたCuを主成分とする第2の導電パターン54と、第2の導電パターン54を構成するアイランド56の上に設けられた半導体素子55と、を備える。半導体素子55には、Cuを主成分とする最表面を有する電極が設けられ、アイランド56と電極の界面は、固相接合により直接固着されている。
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