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Machine translation
1. (WO2013045970) PSEUDO-INVERTER CIRCUIT WITH MULTIPLE INDEPENDENT GATE TRANSISTORS
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2013/045970    International Application No.:    PCT/IB2011/002823
Publication Date: 04.04.2013 International Filing Date: 30.09.2011
IPC:
G11C 8/08 (2006.01), G11C 11/408 (2006.01), H03K 19/20 (2006.01)
Applicants: SOITEC [FR/FR]; Chemin des Franques F-38190 Bernin (FR) (For All Designated States Except US).
MAZURE, Carlos [DE/FR]; (FR) (For US Only).
FERRANT, Richard [FR/FR]; (FR) (For US Only).
NGUYEN, Bich-Yen [US/US]; (US) (For US Only)
Inventors: MAZURE, Carlos; (FR).
FERRANT, Richard; (FR).
NGUYEN, Bich-Yen; (US)
Agent: COLLIN, Jérôme; Cabinet Regimbeau 20, rue de Chazelles F-75847 Paris Cedex 17 (FR)
Priority Data:
Title (EN) PSEUDO-INVERTER CIRCUIT WITH MULTIPLE INDEPENDENT GATE TRANSISTORS
(FR) CIRCUIT PSEUDO-INVERSEUR ÉQUIPÉ DE TRANSISTORS AYANT DE MULTIPLES GRILLES INDÉPENDANTES
Abstract: front page image
(EN)The invention relates to a a circuit including a transistor of a first type of channel in series with a transistor of a second type of channel between first and second terminals for applying a power supply potential, each of the transistors being a multiple gate transistor having at least a first (G1P, G1N) and a second (G2P, G2N) independent control gates, characterized in that at least one of the transistors is configured for operating in a depletion mode under the action of a second gate signal applied to its second control gate (G2p, G2N).
(FR)La présente invention concerne un circuit comportant un transistor ayant un premier type de canal monté en série avec un transistor ayant un second type de canal entre des première et deuxième bornes servant à appliquer un potentiel d'alimentation électrique, chaque transistor étant un transistor à multiples grilles ayant au moins une première (G1P, G1N) et une deuxième (G2P, G2N) grilles de commande indépendantes. Ledit circuit est caractérisé en ce qu'au moins un des transistors est configuré pour fonctionner dans un mode à appauvrissement sous l'action d'un deuxième signal de grille appliqué à sa deuxième grille de commande (G2P, G2N).
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)