Processing

Please wait...

Settings

Settings

Goto Application

1. WO2013036222 - POWER EFFICIENT PROCESSOR ARCHITECTURE

Publication Number WO/2013/036222
Publication Date 14.03.2013
International Application No. PCT/US2011/050580
International Filing Date 06.09.2011
IPC
G06F 15/80 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
15Digital computers in general; Data processing equipment in general
76Architectures of general purpose stored program computers
80comprising an array of processing units with common control, e.g. single instruction multiple data processors
G06F 13/24 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
20for access to input/output bus
24using interrupt
G06F 1/32 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
1Details not covered by groups G06F3/-G06F13/82
26Power supply means, e.g. regulation thereof
32Means for saving power
CPC
G06F 1/3206
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
1Details not covered by groups G06F3/00G06F13/00 and G06F21/00
26Power supply means, e.g. regulation thereof
32Means for saving power
3203Power management, i.e. event-based initiation of power-saving mode
3206Monitoring of events, devices or parameters that trigger a change in power modality
G06F 1/3287
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
1Details not covered by groups G06F3/00G06F13/00 and G06F21/00
26Power supply means, e.g. regulation thereof
32Means for saving power
3203Power management, i.e. event-based initiation of power-saving mode
3234Power saving characterised by the action undertaken
3287by switching off individual functional units in the computer system
G06F 1/3293
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
1Details not covered by groups G06F3/00G06F13/00 and G06F21/00
26Power supply means, e.g. regulation thereof
32Means for saving power
3203Power management, i.e. event-based initiation of power-saving mode
3234Power saving characterised by the action undertaken
3293by switching to a less power-consuming processor, e.g. sub-CPU
G06F 12/084
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
0806Multiuser, multiprocessor or multiprocessing cache systems
084with a shared cache
G06F 13/24
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
20for access to input/output bus
24using interrupt
G06F 2212/1028
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
2212Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
10Providing a specific technical effect
1028Power efficiency
Applicants
  • INTEL CORPORATION [US]/[US] (AllExceptUS)
  • HERDRICH, Andrew, J. [US]/[US] (UsOnly)
  • ILLIKKAL, Rameshkumar, G. [US]/[US] (UsOnly)
  • IYER, Ravishankar [US]/[US] (UsOnly)
  • SRINIVASAN, Sadogopan [IN]/[US] (UsOnly)
  • MOSES, Jaideep [IN]/[US] (UsOnly)
  • MAKINENI, Srihari [US]/[US] (UsOnly)
Inventors
  • HERDRICH, Andrew, J.
  • ILLIKKAL, Rameshkumar, G.
  • IYER, Ravishankar
  • SRINIVASAN, Sadogopan
  • MOSES, Jaideep
  • MAKINENI, Srihari
Agents
  • TROP, Timothy, N.
Priority Data
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) POWER EFFICIENT PROCESSOR ARCHITECTURE
(FR) ARCHITECTURE DE PROCESSEUR À FAIBLE CONSOMMATION D'ÉNERGIE
Abstract
(EN)
In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.
(FR)
Selon un mode de réalisation, la présente invention porte sur un procédé consistant à recevoir une interruption en provenance d'un accélérateur, à émettre un signal de reprise directement à un petit cœur en réponse à l'interruption et à fournir un sous-ensemble d'un état d'exécution du grand cœur au premier petit cœur, et à déterminer si le petit cœur peut ou non traiter une requête associée à l'interruption, et à effectuer une opération correspondant à la requête dans le petit cœur si la détermination est affirmative, et sinon fournir l'état d'exécution du grand cœur et le signal de reprise au grand cœur. D'autres modes de réalisation sont décrits et revendiqués.
Also published as
DE112011105590
DE1120111055900
GB1402807.0
GB1609270.2
GB1609345.2
GB1612629.4
Latest bibliographic data on file with the International Bureau