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1. (WO2013022753) SEMICONDUCTOR DEVICES HAVING FIN STRUCTURES AND FABRICATION METHODS THEREOF
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2013/022753 International Application No.: PCT/US2012/049531
Publication Date: 14.02.2013 International Filing Date: 03.08.2012
IPC:
H01L 29/78 (2006.01) ,H01L 21/336 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
Applicants:
SUVOLTA, INC. [US/US]; 130 D Knowles Drive Los Gatos, CA 95032, US (AllExceptUS)
HOFFMANN, Thomas [FR/US]; US (UsOnly)
THOMPSON, Scott, E. [US/US]; US (UsOnly)
Inventors:
HOFFMANN, Thomas; US
THOMPSON, Scott, E.; US
Agent:
NOVAK DRUCE + QUIGG LLP; Eduardo, J., Quinones City Place Tower 525 Okeechobee Boulevard, 15th Floor West Palm Beach, FL 33401, US
Priority Data:
61/515,45205.08.2011US
Title (EN) SEMICONDUCTOR DEVICES HAVING FIN STRUCTURES AND FABRICATION METHODS THEREOF
(FR) DISPOSITIFS À SEMI-CONDUCTEUR COMPORTANT DES STRUCTURES AILETTES ET PROCÉDÉS DE FABRICATION ASSOCIÉS
Abstract:
(EN) A method of fabricating semiconductor devices includes providing a semiconducting substrate. The method also includes defining a heavily doped region at a surface of the semiconducting substrate in at least one area of the semiconducting substrate, where the heavily doped region includes a heavily doped layer having a doping concentration greater than a doping concentration of the semiconducting substrate. The method also includes forming an additional layer of semiconductor material on the semiconducting substrate, the additional layer comprising a substantially undoped layer. The method further includes applying a first removal process to the semiconducting substrate to define an unetched portion and an etched portion, where the unetched portion defines a fin structure, and the etched portion extends through the additional layer, and then isolating the fin structure from other structures.
(FR) La présente invention concerne un procédé de fabrication de dispositifs à semi-conducteur. Ledit procédé consiste à fournir un substrat semi-conducteur. Le procédé consiste également à définir une région hautement dopée au niveau d'une surface du substrat semi-conducteur dans au moins une zone du substrat semi-conducteur, la région hautement dopée comprenant une couche hautement dopée qui présente une concentration en dopage supérieure à une concentration en dopage du substrat semi-conducteur. Le procédé consiste également à former une couche supplémentaire de matériau semi-conducteur sur le substrat semi-conducteur, la couche supplémentaire comprenant une couche sensiblement non dopée. Le procédé consiste en outre à appliquer un premier procédé de dépose sur le substrat semi-conducteur pour définir une partie non gravée et une partie gravée, la partie non gravée définissant une structure ailette, et la partie gravée s'étendant à travers la couche supplémentaire, et puis à isoler la structure ailette d'autres structures.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
KR1020140050700