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1. WO2013009741 - DE-SKEWED MULTI-DIE PACKAGES

Publication Number WO/2013/009741
Publication Date 17.01.2013
International Application No. PCT/US2012/046049
International Filing Date 10.07.2012
IPC
H01L 25/065 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04the devices not having separate containers
065the devices being of a type provided for in group H01L27/78
G11C 5/06 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
5Details of stores covered by group G11C11/63
06Arrangements for interconnecting storage elements electrically, e.g. by wiring
CPC
G11C 5/06
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
5Details of stores covered by G11C11/00
06Arrangements for interconnecting storage elements electrically, e.g. by wiring
H01L 2224/0401
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
H01L 2224/05554
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
0554External layer
0555Shape
05552in top view
05554being square
H01L 2224/06135
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
06of a plurality of bonding areas
061Disposition
0612Layout
0613Square or rectangular array
06134covering only portions of the surface to be connected
06135Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
H01L 2224/06136
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
06of a plurality of bonding areas
061Disposition
0612Layout
0613Square or rectangular array
06134covering only portions of the surface to be connected
06136Covering only the central area of the surface to be connected, i.e. central arrangements
H01L 2224/12105
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
10Bump connectors; Manufacturing methods related thereto
12Structure, shape, material or disposition of the bump connectors prior to the connecting process
12105Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
Applicants
  • TESSERA, INC. [US]/[US] (AllExceptUS)
  • CRISP, Richard Dewitt [US]/[US] (UsOnly)
  • HABA, Belgacem [US]/[US] (UsOnly)
  • ZOHNI, Wael [US]/[US] (UsOnly)
Inventors
  • CRISP, Richard Dewitt
  • HABA, Belgacem
  • ZOHNI, Wael
Agents
  • NEFF, Daryl, K.
Priority Data
13/306,06829.11.2011US
61/506,88912.07.2011US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) DE-SKEWED MULTI-DIE PACKAGES
(FR) BOÎTIERS POUR PUCES MULTIPLES AVEC REDRESSEMENT
Abstract
(EN)
A microelectronic package (10) may have a plurality of terminals (36) disposed at a face (32) thereof which are configured for connection to at least one external component, e.g., a circuit panel (70). First and second microelectronic elements (12), (14) can be affixed with packaging structure (30) therein. A first electrical connection (51A, 40A, 74A) can extend from a respective terminal (36A) of the package (10) to a corresponding contact (20A) on the first microelectronic element (12), and a second electrical connection (53A, 40B, 52A) can extend from the respective terminal (36A) to a corresponding contact (26A) on the second microelectronic element (14), the first and second connections being configured such that a respective signal carried by the first and second connections is subject to propagation delay of the same duration between the respective terminal (36A) and each of the corresponding contacts (20A, 26A) coupled thereto.
(FR)
La présente invention concerne un boîtier microélectronique (10) qui peut posséder une pluralité de bornes (36) disposées sur une face (32) de celui-ci et configurées pour être connectées à au moins un composant extérieur, par exemple un panneau de circuits (70). Des premier et second éléments microélectroniques (12, 14) peuvent être fixés avec une structure de conditionnement (30) dans celui-ci. Une première connexion électrique (51A, 40A, 74A) peut s'étendre d'une borne respective (36A) du boîtier (10) à un contact correspondant (20A) sur le premier élément microélectronique (12) et une seconde connexion électrique (53A, 40B, 52A) peut s'étendre de la borne respective (36A) à un contact correspondant (26A) sur le second élément microélectronique (14), la première et la seconde connexion étant configurées de telle sorte qu'un signal respectif transporté par la première et la seconde connexion est soumis à un retard de propagation de même durée entre la borne respective (36A) et chacun des contacts correspondants (20A, 26A) couplés à celle-ci.
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