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1. WO2013008414 - RECTIFIER DEVICE

Publication Number WO/2013/008414
Publication Date 17.01.2013
International Application No. PCT/JP2012/004319
International Filing Date 04.07.2012
IPC
H01L 29/47 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40Electrodes
43characterised by the materials of which they are formed
47Schottky barrier electrodes
H01L 29/872 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66Types of semiconductor device
86controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated, or switched
861Diodes
872Schottky diodes
CPC
H01L 2224/04042
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
04042Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
H01L 2224/05553
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
0554External layer
0555Shape
05552in top view
05553being rectangular
H01L 2224/45124
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
44Structure, shape, material or disposition of the wire connectors prior to the connecting process
45of an individual wire connector
45001Core members of the connector
45099Material
451with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
45117the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
45124Aluminium (Al) as principal constituent
H01L 2224/45147
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
44Structure, shape, material or disposition of the wire connectors prior to the connecting process
45of an individual wire connector
45001Core members of the connector
45099Material
451with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
45138the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
45147Copper (Cu) as principal constituent
H01L 2224/48091
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
47Structure, shape, material or disposition of the wire connectors after the connecting process
48of an individual wire connector
4805Shape
4809Loop shape
48091Arched
H01L 2224/48247
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
47Structure, shape, material or disposition of the wire connectors after the connecting process
48of an individual wire connector
481Disposition
48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
48221the body and the item being stacked
48245the item being metallic
48247connecting the wire to a bond pad of the item
Applicants
  • パナソニック株式会社 PANASONIC CORPORATION [JP]/[JP] (AllExceptUS)
  • 井腰 文智 IKOSHI, Ayanori (UsOnly)
  • 橋詰 真吾 HASHIZUME, Shingo (UsOnly)
  • 山際 優人 YAMAGIWA, Hiroto (UsOnly)
Inventors
  • 井腰 文智 IKOSHI, Ayanori
  • 橋詰 真吾 HASHIZUME, Shingo
  • 山際 優人 YAMAGIWA, Hiroto
Agents
  • 新居 広守 NII, Hiromori
Priority Data
2011-15220908.07.2011JP
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) RECTIFIER DEVICE
(FR) DISPOSITIF REDRESSEUR
(JA) 整流装置
Abstract
(EN)
The present invention fabricates a rectifier device in which current collapse is reduced. A rectifier device (100) provided with: a semiconductor layer laminate having a first nitride semiconductor layer (109) formed on the main surface of a substrate (107), a second nitride semiconductor layer (110) formed on the first nitride semiconductor layer (109) and having a larger band gap than the first nitride semiconductor layer (109), and a channel in which electrons travel in the direction that is parallel to the main surface of the substrate (107); an anode electrode (102a) formed on the semiconductor layer laminate and coming into Schottky contact with the semiconductor layer laminate; a plurality of cathode electrodes (103a) formed on the semiconductor layer laminate with a predetermined distance from the anode electrode (102a) and coming into ohmic contact with the semiconductor layer laminate; and a substrate electrode (lead frame (112)) formed on the rear surface of the substrate (107). The substrate electrode is grounded to a potential of 0V or more.
(FR)
La présente invention concerne un dispositif redresseur caractérisé par une réduction de l'effondrement du courant. Un dispositif redresseur (100) selon l'invention comporte : un stratifié de couches semiconductrices comprenant une première couche semiconductrice (109) au nitrure formée sur la surface principale d'un substrat (107), une deuxième couche semiconductrice (110) au nitrure formée sur la première couche semiconductrice (109) au nitrure et présentant une bande interdite plus importante que celle de la première couche semiconductrice (109) au nitrure, et un canal dans lequel des électrons circulent dans une direction parallèle à la surface principale du substrat (107) ; une électrode (102a) d'anode formée sur le stratifié de couches semiconductrices et entrant en contact de Schottky avec le stratifié de couches semiconductrices ; une pluralité d'électrodes (103a) de cathode formées sur le stratifié de couches semiconductrices à une distance prédéterminée de l'électrode (102a) d'anode et entrant en contact ohmique avec le stratifié de couches semiconductrices ; et une électrode de substrat (grille (112) de connexion) formée sur la surface arrière du substrat (107). L'électrode de substrat est mise à la masse à un potentiel de 0V ou plus.
(JA)
 電流コラプスを低減した整流装置を実現する。整流装置(100)は、基板(107)の主面の上に形成された第1の窒化物半導体層(109)と、第1の窒化物半導体層(109)の上に形成され、かつ、第1の窒化物半導体層(109)に比べてバンドギャップが大きい第2の窒化物半導体層(110)とを有し、基板(107)の主面と平行な方向に電子が走行するチャネルを有する半導体層積層体と、半導体層積層体に形成され、半導体層積層体とショットキー接触するアノード電極(102a)と、半導体層積層体にアノード電極(102a)と所定の間隔をおいて形成され、半導体層積層体とオーミック接触する複数のカソード電極(103a)と、基板(107)の裏面に形成された基板電極(リードフレーム(112))とを備え、基板電極は0V以上の電位に接地される。
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