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1. WO2013007229 - MONOLITHIC INTEGRATED SEMICONDUCTOR STRUCTURE

Publication Number WO/2013/007229
Publication Date 17.01.2013
International Application No. PCT/DE2012/000589
International Filing Date 25.04.2012
IPC
H01L 21/02 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
CPC
H01L 21/02381
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
02104Forming layers
02365Forming inorganic semiconducting materials on a substrate
02367Substrates
0237Materials
02373Group 14 semiconducting materials
02381Silicon, silicon germanium, germanium
H01L 21/02458
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
02104Forming layers
02365Forming inorganic semiconducting materials on a substrate
02436Intermediate layers between substrates and deposited layers
02439Materials
02455Group 13/15 materials
02458Nitrides
H01L 21/02461
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
02104Forming layers
02365Forming inorganic semiconducting materials on a substrate
02436Intermediate layers between substrates and deposited layers
02439Materials
02455Group 13/15 materials
02461Phosphides
H01L 21/02463
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
02104Forming layers
02365Forming inorganic semiconducting materials on a substrate
02436Intermediate layers between substrates and deposited layers
02439Materials
02455Group 13/15 materials
02463Arsenides
H01L 21/02466
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
02104Forming layers
02365Forming inorganic semiconducting materials on a substrate
02436Intermediate layers between substrates and deposited layers
02439Materials
02455Group 13/15 materials
02466Antimonides
H01L 21/02505
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
02104Forming layers
02365Forming inorganic semiconducting materials on a substrate
02436Intermediate layers between substrates and deposited layers
02494Structure
02496Layer structure
02505consisting of more than two layers
Applicants
  • NASP III/V GMBH [DE]/[DE] (AllExceptUS)
  • KUNERT, Bernadette [DE]/[DE] (UsOnly)
Inventors
  • KUNERT, Bernadette
Agents
  • JUNGBLUT, Bernhard
Priority Data
10 2011 107 657.712.07.2011DE
Publication Language German (DE)
Filing Language German (DE)
Designated States
Title
(DE) MONOLITHISCHE INTEGRIERTE HALBLEITERSTRUKTUR
(EN) MONOLITHIC INTEGRATED SEMICONDUCTOR STRUCTURE
(FR) STRUCTURE SEMI-CONDUCTRICE MONOLITHIQUE INTÉGRÉE
Abstract
(DE)
Die Erfindung betrifft eine monolithische integrierte Halbleiterstruktur enthaltend den folgenden Schichtaufbau: A) eine Trägerschicht auf Basis dotiertem oder undotiertem Si, B) optional einer Schicht mit der Zusammensetzung BxAlyGazNtPv, wobei x=0-0,1, y=0-1, z=0-1, t=0-0,1 und v=0,9-1, C) einer Relaxationsschicht mit der Zusammensetzung BxAlyGazInuPvSbw, wobei x=0-0,1, y=0-1, z=0-1, u=0-1, v=0-1 und w=0-1, wobei w und/oder u auf der der Schicht A) oder B) zugewandten Seite kleiner, gleich, oder größer als auf der der Schicht A) oder B) abgewandten Seite ist, und wobei v=1-w und/oder y=1-u-x-z, D) optional einer Schicht zur Blockierung von Fehlversetzungen mit der Zusammensetzung BxAlyGazInuPvSbwNt, wobei x=0-0,1, y=0-1, z=0-1, u=0-1, v=0-1, w=0-1 und t=0-0,1, E) optional einer Schicht zum Hetero-offset mit der Zusammensetzung BxAlyGazInuPvSbwNtAsr wobei x=0-0,1, y=0-1, z=0-1, u=0-1, v=0-1, w=0-1, t=0-0,1 und r=0-1, und F) ein beliebiges, vorzugsweise Gruppe III/V, Halbleitermaterial, oder eine Kombination von mehreren verschiedenen beliebigen Halbleitermaterialien, wobei die vorstehenden stöchiometrischen Indizes für alle Gruppe III Elemente in der Summe stets 1 ergeben und wobei die vorstehenden stöchiometrischen Indizes für alle Gruppe V Elemente in der Summe ebenfalls stets 1 ergeben.
(EN)
The invention relates to a monolithic integrated semiconductor structure containing the following layer structure: A) a substrate layer based on doped or undoped Si; B) optionally a layer having the composition BxAlyGazNtPv, wherein x=0-0.1, y=0-1, z=0-1, t=0-0.1, and v=0.9-1; C) a relaxation layer having the composition BxAlyGazInuPvSbw, wherein x=0-0.1, y=0-1, z=0-1, u=0-1, v=0-1, and w=0-1, wherein w and/or u on the side facing layer A) or B) are/is less than, equal to or greater than on the side facing away from layer A) or B), and wherein v=1-w and/or y=1-u-x-z; D) optionally a layer for blocking misfit dislocations having the composition BxAlyGazInuPvSbwNt, wherein x=0-0.1, y=0-1, z=0-1, u=0-1, v=0-1, w=0-1 and t=0-0.1; E) optionally a layer for the hetero offset having the composition BxAlyGazInuPvSbwNtAsr, wherein x=0-0.1, y=0-1, z=0-1, u=0-1, v=0-1, w=0-1, t=0-0.1 and r=0-1; and F) an arbitrary, preferably group III/V, semiconductor material, or a combination of several different arbitrary semiconductor materials, wherein the above stoichiometric indices for all group III elements always result in 1 in sum, and wherein the above stoichiometric indices for all group V elements likewise always result in 1 in sum.
(FR)
L'invention concerne une structure semi-conductrice monolithique intégrée comprenant les couches suivantes: A) une couche support à base de Si dopé ou non, B) éventuellement une couche de composition BxAlyGazNtPv, sachant que x=0-0,1, y=0-1, z=0-1, t=0-0,1 et v=0,9-1, C) une couche de relaxation, de composition BxAlyGazInuPvSbw, sachant que x=0-0,1, y=0-1, z=0-1, u=0-1, v=0-1 et w=0-1, w et/ou u sur la face orientée vers la couche A) ou B) étant plus petits, égaux ou plus grands que sur la face opposée à la couche A) ou B), et v=1-w et/ou y=1-u-x-z, D) éventuellement une couche destinée à bloquer des dislocations, de composition BxAlyGazInuPvSbwNt, sachant que x=0-0,1, y=0-1, z=0-1, u=0-1, v=0-1, w=0-1 et t=0-0,1, E) éventuellement une couche destinée à la discontinuité hétérogène, de composition BxAlyGazInuPvSbwNtAsr sachant que x=0-0,1, y=0-1, z=0-1, u=0-1, v=0-1, w=0-1, t=0-0,1 et r=0-1, et F) un matériau semi-conducteur quelconque, de préférence de groupe III/V, ou une combinaison de plusieurs matériaux semi-conducteurs différents quelconques, les indices stoechiométriques cités donnant toujours une somme égale à 1 pour tous les éléments du groupe III, et les indices stoechiométriques cités donnant également toujours une somme égale à 1 pour tous les éléments du groupe V.
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