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1. WO2013006211 - METHOD AND APPARATUS FOR SELF-ANNEALING MULTI-DIE INTERCONNECT REDUNDANCY CONTROL

Publication Number WO/2013/006211
Publication Date 10.01.2013
International Application No. PCT/US2012/024345
International Filing Date 08.02.2012
Chapter 2 Demand Filed 04.05.2012
IPC
H03K 19/177 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
02using specified components
173using elementary logic circuits as components
177arranged in matrix form
H03K 19/003 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
003Modifications for increasing the reliability
H01L 21/66 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
66Testing or measuring during manufacture or treatment
CPC
H01L 22/14
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
22Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
10Measuring as part of the manufacturing process
14for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
H01L 22/22
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
22Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
20Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
22Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement
H01L 2224/14515
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
10Bump connectors; Manufacturing methods related thereto
12Structure, shape, material or disposition of the bump connectors prior to the connecting process
14of a plurality of bump connectors
1451Function
14515Bump connectors having different functions
H01L 2224/16145
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
10Bump connectors; Manufacturing methods related thereto
15Structure, shape, material or disposition of the bump connectors after the connecting process
16of an individual bump connector
161Disposition
16135the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
16145the bodies being stacked
H01L 24/14
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
24Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
10Bump connectors
12Structure, shape, material or disposition of the bump connectors prior to the connecting process
14of a plurality of bump connectors
H03K 19/00392
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output
003Modifications for increasing the reliability ; for protection
00392by circuit redundancy
Applicants
  • XILINX, INC. [US]/[US] (AllExceptUS)
  • CAMAROTA, Rafael, C. [US]/[US] (UsOnly)
Inventors
  • CAMAROTA, Rafael, C.
Agents
  • CARTIER, Lois, D.
Priority Data
13/176,58605.07.2011US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) METHOD AND APPARATUS FOR SELF-ANNEALING MULTI-DIE INTERCONNECT REDUNDANCY CONTROL
(FR) PROCÉDÉ ET APPAREIL POUR LA COMMANDE DE REDONDANCE D'INTERCONNEXION ENTRE PUCES MULTIPLES, AVEC RECUIT AUTOMATIQUE
Abstract
(EN)
An apparatus for interconnecting a first die (402) and a second die (404) of a multi-die device (400) includes a master circuit block (406) that interfaces with the first die of the multi-die device, a slave circuit block (408) that interfaces with the second die of the multi-die device, a first memory (416a-416e) in the slave circuit block, a second memory (430a-430e) in the master circuit block, and a plurality of μbumps (1 -6) between the first die and the second die, wherein the master circuit block and the slave circuit block are configured to identify one of the μbumps (3) as a faulty μbump, and store a first value that corresponds with the identified faulty μbump in the first memory.
(FR)
L'invention concerne un appareil destiné à interconnecter une première puce (402) et une seconde puce (404) dans un dispositif à puces multiples (400), comprenant un bloc de circuits maître (406) qui s'interface avec la première puce du dispositif à puces multiples, un bloc de circuits esclave (408) qui s'interface avec la seconde puce du dispositif à puces multiples, une première mémoire (416a à 416e) sur le bloc de circuits esclave, une seconde mémoire (430a à 430e) sur le bloc de circuits maître et une pluralité de microbosses (1 à 6) entre la première puce et la seconde puce. Le bloc de circuits maître et le bloc de circuits esclave sont configurés pour identifier l'une des microbosses (3) comme défectueuse et pour stocker une première valeur qui correspond à la microbosse défectueuse identifiée dans la première mémoire.
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