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1. (WO2012177368) BIT SCAN CIRCUIT AND METHOD IN NON-VOLATILE MEMORY
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2012/177368 International Application No.: PCT/US2012/040145
Publication Date: 27.12.2012 International Filing Date: 31.05.2012
IPC:
G11C 29/40 (2006.01) ,G11C 29/44 (2006.01)
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
29
Checking stores for correct operation; Testing stores during standby or offline operation
04
Detection or location of defective memory elements
08
Functional testing, e.g. testing during refresh, power-on self testing (POST) or distributed testing
12
Built-in arrangements for testing, e.g. built-in self testing (BIST)
38
Response verification devices
40
using compression techniques
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
29
Checking stores for correct operation; Testing stores during standby or offline operation
04
Detection or location of defective memory elements
08
Functional testing, e.g. testing during refresh, power-on self testing (POST) or distributed testing
12
Built-in arrangements for testing, e.g. built-in self testing (BIST)
44
Indication or identification of errors, e.g. for repair
Applicants:
SANDISK TECHNOLOGIES INC. [US/US]; Two Legacy Town Center 6900 North Dallas Parkway Plano, Texas 75024, US (AllExceptUS)
LIU, Bo [CN/US]; US (UsOnly)
PARK, Jongmin [KR/US]; US (UsOnly)
CHEN, Chen [US/US]; US (UsOnly)
KUO, Tien-Chien [CN/US]; US (UsOnly)
Inventors:
LIU, Bo; US
PARK, Jongmin; US
CHEN, Chen; US
KUO, Tien-Chien; US
Agent:
YAU, Philip; Davis Wright Tremaine LLP 505 Montgomery Street, Suite 800 San Francisco, California 94111, US
Priority Data:
13/164,61820.06.2011US
Title (EN) BIT SCAN CIRCUIT AND METHOD IN NON-VOLATILE MEMORY
(FR) CIRCUIT DE SCRUTATION DE BITS ET PROCÉDÉ DANS UNE MÉMOIRE NON VOLATILE
Abstract:
(EN) A circuit (150) for counting in an N-bit string (10) a number of bits M, having a first binary value includes N latch circuits in a daisy chain (100) where each latch circuit has a tag bit that controls each to be either in a no-pass or pass state. Initially the tag bits are set according to the bits of the N-bit string where the first binary value corresponds to a no-pass state. A clock signal having a pulse train is run through the daisy chain to "interrogate" any no-pass latch circuits. It races right through any pass latch circuit. However, for a no-pass latch circuit, a leading pulse while being blocked also resets after a pulse period the tag bit from "no-pass" to "pass" state to allow subsequent pulses to pass. After all no-pass latch circuits have been reset, M is given by the number of missing pulses from the pulse train.
(FR) La présente invention concerne un circuit (150) servant à compter dans une chaîne de N bits (10) un certain nombre de bits M, ayant une première valeur binaire. Ledit circuit comporte N circuits verrous formant une guirlande (100), chaque circuit verrou a un bit de balise qui commande chaque circuit pour qu'il soit dans un état non passant ou passant. Initialement, les bits de balise sont définis selon les bits de la chaîne de N bits où la première valeur binaire correspond à un état non passant. Un signal d'horloge ayant un train d'impulsions traverse la guirlande pour « interroger » les circuits verrous non passants. Il traverse les circuits verrous passants. Toutefois, pour un circuit verrou non passant, une impulsion de tête, lorsqu'elle est bloquée, remet également après une période d'impulsion le bit de balise de l'état « non passant » à l'état « passant » pour permettre aux impulsions suivantes de passer. Après que tous les circuits verrous non passants ont été remis à l'état « passant », M est donné par le nombre d'impulsions manquantes du train d'impulsions.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
KR1020140057499CN103733263