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1. (WO2012176452) SEMICONDUCTOR RECORDING DEVICE
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2012/176452 International Application No.: PCT/JP2012/004024
Publication Date: 27.12.2012 International Filing Date: 21.06.2012
IPC:
G11C 13/00 (2006.01) ,H01L 27/10 (2006.01) ,H01L 27/105 (2006.01) ,H01L 45/00 (2006.01) ,H01L 49/00 (2006.01)
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
13
Digital stores characterised by the use of storage elements not covered by groups G11C11/, G11C23/, or G11C25/173
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
105
including field-effect components
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
45
Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
49
Solid state devices not provided for in groups H01L27/-H01L47/99; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
Applicants:
パナソニック株式会社 PANASONIC CORPORATION [JP/JP]; 大阪府門真市大字門真1006番地 1006, Oaza Kadoma, Kadoma-shi, Osaka 5718501, JP (AllExceptUS)
山平 征二 YAMAHIRA, Seiji; null (UsOnly)
Inventors:
山平 征二 YAMAHIRA, Seiji; null
Agent:
新居 広守 NII, Hiromori; 大阪府大阪市淀川区西中島5丁目3番10号タナカ・イトーピア新大阪ビル6階新居国際特許事務所内 c/o NII Patent Firm, 6F, Tanaka Ito Pia Shin-Osaka Bldg.,3-10, Nishi Nakajima 5-chome, Yodogawa-ku, Osaka-city, Osaka 5320011, JP
Priority Data:
2011-14008324.06.2011JP
Title (EN) SEMICONDUCTOR RECORDING DEVICE
(FR) DISPOSITIF D'ENREGISTREMENT À SEMI-CONDUCTEURS
(JA) 半導体記憶装置
Abstract:
(EN) Provided is a semiconductor recording device in which even when the ambient temperature has changed it is easy to guarantee a read-out margin. The device is provided with: a memory cell (901) which includes a first variable resistance element having a variable electrical resistance; a first reference cell (107) which includes a second variable resistance element having a variable electrical resistance, and which is the standard for the determination of the size of the electrical resistance of the memory cell; and a second reference cell (108) which is the standard for the determination of the size of the electrical resistance of the first reference cell. Therein, the temperature coefficient of the first variable resistance element and the temperature coefficient of the second variable resistance element are of the same polarity.
(FR) L'invention concerne un dispositif d'enregistrement à semi-conducteurs qui permet de garantir facilement une marge de lecture même lorsque la température ambiante a changé. Le dispositif comprend : une cellule de mémoire (901) qui comprend un premier élément de résistance variable ayant une résistance électrique variable ; une première cellule de référence (107) qui comprend un second élément de résistance variable ayant une résistance électrique variable, et qui constitue la norme pour déterminer la taille de la résistance électrique de la cellule de mémoire ; et une seconde cellule de référence (108) qui constitue la norme pour déterminer la taille de la résistance électrique de la première cellule de référence. Le coefficient de température du premier élément de résistance variable et le coefficient de température du second élément de résistance variable sont de la même polarité.
(JA)  周辺温度が変化したときの読出しマージンの確保がしやすい半導体記憶装置を提供する。 電気抵抗が変化する第1の抵抗変化素子を含むメモリセル(901)と、メモリセルの電気抵抗の大きさの判定基準となり、電気抵抗が変化する第2の抵抗変化素子を含む第1のリファレンスセル(107)と、第1のリファレンスセルの電気抵抗の大きさの判定基準となる第2のリファレンスセル(108)と、を備え、第1の抵抗変化素子の温度係数と第2の抵抗変化素子の温度係数とが同じ極性である。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)
Also published as:
JPWO2012176452